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binutils-apple
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WIP MachO binutils port assisted by AI I may consider upstreaming this in the future.
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binutils-apple
/
sim
/
testsuite
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at
master
31 folders
3 files
Tom Tromey
Update copyright dates to include 2026
6mo ago
4abc1ce2
aarch64
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
arm
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
avr
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
bfin
[sim] Run spellcheck.sh in sim (part 1) Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
2 years ago
bpf
sim: bpf: remove support for ldinddw and ldabsdw instructions This patch removes support for the two instructions above from the GNU simulator, including the corresponding tests. These instructions do not really exist in BPF and are not recognized as such by the kernel verifier. This has now been pointed out during the standardization of the BPF ISA. Signed-off-by: Jose E. Marchesi <jose.marchesi@oracle.com>
2 years ago
common
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
config
sim: testsuite: rework sim_init usage The sim_init function was called by runtest for each test when --tool was set to sim. When we changed to --tool '' to collapse the testsuite dir, the init function was no longer called on every test. However, it was still being called explicitly by config/default.exp. It's not clear why that explicit call ever existed since, in the past, it meant it was redundant. Lets drop the single sim_init call in config/default.exp and move it out to all our tests. This replicates the runtest behavior so we can setup variables on a per-test basis which allows us to recollapse the sim_path logic back. We'll also leverage this in the future for toolchain setup. Also add a few comments clarifying the overall runtime behavior.
4 years ago
cr16
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
cris
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
d10v
[sim] Run spellcheck.sh in sim (part 1) Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
2 years ago
example-synacor
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
frv
[sim] Run spellcheck.sh in sim (part 1) Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
2 years ago
ft32
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
h8300
[sim] Run spellcheck.sh in sim (part 1) Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
2 years ago
iq2000
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
lib
sim prune_warnings Remove some of the warnings generated by newer versions of ld. * testsuite/lib/sim-defs.exp (prune_warnings_extra): New. Arrange to run it from prune_warnings.
2 years ago
lm32
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
m32c
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
m32r
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
m68hc11
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
mcore
Yet another fix for mcore-sim (rotli) This came up testing the CRC optimization work from Mariam@RAU. Basically to optimize some CRC loops into table lookups or carryless multiplies, we may need to do a bit reflection, which on the mcore processor is done using a rotate instruction. Unfortunately the simulator implementation of rotates has the exact same problem as we saw with right shifts. The input value may have been sign extended from 32 to 64 bits. When we rotate the extended value, we get those sign extension bits and thus the wrong result. The fix is the same. Rather than using a "long", use a uint32_t for the type of the temporary. This fixes a handful of tests in the GCC testsuite:
2 years ago
microblaze
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
mips
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
mn10300
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
moxie
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
msp430
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
or1k
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
pru
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
riscv
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
sh
sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.
5 years ago
v850
Fix for v850e divq instruction This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch.
4 years ago
.gitignore
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago
ChangeLog-2021
sim: rename ChangeLog files to ChangeLog-2021 Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree.
5 years ago
local.mk
Update copyright dates to include 2026 This updates the copyright headers to include 2026. I did this by running gdb/copyright.py and then manually modifying a few files as noted by the script.
6 months ago