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WIP MachO binutils port assisted by AI I may consider upstreaming this in the future.
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binutils-apple
/
sim
/
testsuite
/
riscv
/
at
master
7 files
Jaydeep Patil
sim: riscv: Add support for compressed integer instructions
2y ago
3224e32f
ChangeLog-2021
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
allinsn.exp
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
c-ext.s
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
jalr.s
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
m-ext.s
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
pass.s
sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago
testutils.inc
sim/riscv: fix JALR instruction simulation Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>
2 years ago