opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
2005-10-08 Paul Brook <paul@codesourcery.com>
bfd/
* elf32-arm.c: Move #include "elf/arm.h" after libbfd.h.
(NUM_KNOWN_ATTRIBUTES): Define.
(aeabi_attribute, aeabi_attribute_list): Define.
(elf32_arm_obj_tdata): Add known_eabi_attributes and
other_eabi_attributes.
(uleb128_size, is_default_attr, eabi_attr_size,
elf32_arm_eabi_attr_size, write_uleb128, write_eabi_attribute,
elf32_arm_set_eabi_attr_contents, elf32_arm_bfd_final_link,
elf32_arm_new_eabi_attr, attr_strdup, elf32_arm_add_eabi_attr_int,
elf32_arm_add_eabi_attr_compat, copy_eabi_attributes,
elf32_arm_merge_eabi_attributes): New functions.
(elf32_arm_copy_private_bfd_data): Copy EABI object attributes.
(elf32_arm_fake_sections): Handle .ARM.attributes.
(elf32_arm_parse_attributes): New function.
(elf32_arm_section_from_shdr): Use it.
(bfd_elf32_bfd_final_link): Define.
gas/
* config/tc-arm.c: Don't provide fallback default for CPU_DEFAULT.
(arm_arch_used, thumb_arch_used, selected_cpu, selected_cpu_name):
New variables.
(arm_cpu_option_table): Add canonical_name.
(arm_cpus): Populate canonical_name field.
(s_arm_eabi_attribute, s_arm_arch, s_arm_cpu, s_arm_fpu,
aeabi_set_public_attributes, arm_md_end): New functions.
(md_pseudo_table): Add "cpu", "arch", "fpu" and "eabi_attribute".
(md_assemble): Set thumb_arch_used and arm_arch_used.
(md_begin): Set defaut cpu if CPU_DEFAULT not defined.
* config/tc-arm.h (md_end): Define.
* doc/c-arm.texi: Document .cpu, .arch, .fpu and .eabi_attribute.
gas/testsuite/
* gas/arm/eabi_attr_1.s: New test.
* gas/arm/eabi_attr_1.d: New test.
* gas/arm/arm7t.d: Only disassemble code sections.
* gas/arm/bignum1.d: Ignore Arm object attribute sections.
* gas/arm/mapping.d: Ditto.
* gas/arm/unwind.d: Ditto.
* gas/elf/section0.d: Ditto.
* gas/elf/section1.d: Ditto.
* gas/elf/elf.exp: Set target_machine for Arm EABI based targets.
* gas/elf/section2.e-armeabi: New file.
include/elf/
* arm.h: Add prototypes for BFD object attribute routines.
ld/testsuite/
* ld-arm/arm-rel31.d: Ignore Arm object attribute sections.
* ld-arm/arm-target1-abs.d: Ditto.
* ld-arm/arm-target1-rel.d: Ditto.
* ld-arm/arm-target2-abs.d: Ditto.
* ld-arm/arm-target2-got-rel.d: Ditto.
* ld-arm/arm-target2-rel.d: Ditto.
2005-10-08 Paul Brook <paul@codesourcery.com>
bfd/
* elf32-arm.c: Move #include "elf/arm.h" after libbfd.h.
(NUM_KNOWN_ATTRIBUTES): Define.
(aeabi_attribute, aeabi_attribute_list): Define.
(elf32_arm_obj_tdata): Add known_eabi_attributes and
other_eabi_attributes.
(uleb128_size, is_default_attr, eabi_attr_size,
elf32_arm_eabi_attr_size, write_uleb128, write_eabi_attribute,
elf32_arm_set_eabi_attr_contents, elf32_arm_bfd_final_link,
elf32_arm_new_eabi_attr, attr_strdup, elf32_arm_add_eabi_attr_int,
elf32_arm_add_eabi_attr_compat, copy_eabi_attributes,
elf32_arm_merge_eabi_attributes): New functions.
(elf32_arm_copy_private_bfd_data): Copy EABI object attributes.
(elf32_arm_fake_sections): Handle .ARM.attributes.
(elf32_arm_parse_attributes): New function.
(elf32_arm_section_from_shdr): Use it.
(bfd_elf32_bfd_final_link): Define.
gas/
* config/tc-arm.c: Don't provide fallback default for CPU_DEFAULT.
(arm_arch_used, thumb_arch_used, selected_cpu, selected_cpu_name):
New variables.
(arm_cpu_option_table): Add canonical_name.
(arm_cpus): Populate canonical_name field.
(s_arm_eabi_attribute, s_arm_arch, s_arm_cpu, s_arm_fpu,
aeabi_set_public_attributes, arm_md_end): New functions.
(md_pseudo_table): Add "cpu", "arch", "fpu" and "eabi_attribute".
(md_assemble): Set thumb_arch_used and arm_arch_used.
(md_begin): Set defaut cpu if CPU_DEFAULT not defined.
* config/tc-arm.h (md_end): Define.
* doc/c-arm.texi: Document .cpu, .arch, .fpu and .eabi_attribute.
gas/testsuite/
* gas/arm/eabi_attr_1.s: New test.
* gas/arm/eabi_attr_1.d: New test.
* gas/arm/arm7t.d: Only disassemble code sections.
* gas/arm/bignum1.d: Ignore Arm object attribute sections.
* gas/arm/mapping.d: Ditto.
* gas/arm/unwind.d: Ditto.
* gas/elf/section0.d: Ditto.
* gas/elf/section1.d: Ditto.
* gas/elf/elf.exp: Set target_machine for Arm EABI based targets.
* gas/elf/section2.e-armeabi: New file.
include/elf/
* arm.h: Add prototypes for BFD object attribute routines.
ld/testsuite/
* ld-arm/arm-rel31.d: Ignore Arm object attribute sections.
* ld-arm/arm-target1-abs.d: Ditto.
* ld-arm/arm-target1-rel.d: Ditto.
* ld-arm/arm-target2-abs.d: Ditto.
* ld-arm/arm-target2-got-rel.d: Ditto.
* ld-arm/arm-target2-rel.d: Ditto.
2005-10-08 Paul Brook <paul@codesourcery.com>
bfd/
* elf32-arm.c: Move #include "elf/arm.h" after libbfd.h.
(NUM_KNOWN_ATTRIBUTES): Define.
(aeabi_attribute, aeabi_attribute_list): Define.
(elf32_arm_obj_tdata): Add known_eabi_attributes and
other_eabi_attributes.
(uleb128_size, is_default_attr, eabi_attr_size,
elf32_arm_eabi_attr_size, write_uleb128, write_eabi_attribute,
elf32_arm_set_eabi_attr_contents, elf32_arm_bfd_final_link,
elf32_arm_new_eabi_attr, attr_strdup, elf32_arm_add_eabi_attr_int,
elf32_arm_add_eabi_attr_compat, copy_eabi_attributes,
elf32_arm_merge_eabi_attributes): New functions.
(elf32_arm_copy_private_bfd_data): Copy EABI object attributes.
(elf32_arm_fake_sections): Handle .ARM.attributes.
(elf32_arm_parse_attributes): New function.
(elf32_arm_section_from_shdr): Use it.
(bfd_elf32_bfd_final_link): Define.
gas/
* config/tc-arm.c: Don't provide fallback default for CPU_DEFAULT.
(arm_arch_used, thumb_arch_used, selected_cpu, selected_cpu_name):
New variables.
(arm_cpu_option_table): Add canonical_name.
(arm_cpus): Populate canonical_name field.
(s_arm_eabi_attribute, s_arm_arch, s_arm_cpu, s_arm_fpu,
aeabi_set_public_attributes, arm_md_end): New functions.
(md_pseudo_table): Add "cpu", "arch", "fpu" and "eabi_attribute".
(md_assemble): Set thumb_arch_used and arm_arch_used.
(md_begin): Set defaut cpu if CPU_DEFAULT not defined.
* config/tc-arm.h (md_end): Define.
* doc/c-arm.texi: Document .cpu, .arch, .fpu and .eabi_attribute.
gas/testsuite/
* gas/arm/eabi_attr_1.s: New test.
* gas/arm/eabi_attr_1.d: New test.
* gas/arm/arm7t.d: Only disassemble code sections.
* gas/arm/bignum1.d: Ignore Arm object attribute sections.
* gas/arm/mapping.d: Ditto.
* gas/arm/unwind.d: Ditto.
* gas/elf/section0.d: Ditto.
* gas/elf/section1.d: Ditto.
* gas/elf/elf.exp: Set target_machine for Arm EABI based targets.
* gas/elf/section2.e-armeabi: New file.
include/elf/
* arm.h: Add prototypes for BFD object attribute routines.
ld/testsuite/
* ld-arm/arm-rel31.d: Ignore Arm object attribute sections.
* ld-arm/arm-target1-abs.d: Ditto.
* ld-arm/arm-target1-rel.d: Ditto.
* ld-arm/arm-target2-abs.d: Ditto.
* ld-arm/arm-target2-got-rel.d: Ditto.
* ld-arm/arm-target2-rel.d: Ditto.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
arm, objdump: Make objdump use bfd's machine detection to drive disassembly
For any arm elf target, disable an old piece of code that forced disassembly to
disassemble for 'unknown architecture' which once upon a time meant it would
disassemble ANY arm instruction. This is no longer true with the addition of
Armv8.1-M Mainline, as there are conflicting encodings for different thumb
instructions.
BFD however can detect what architecture the object file was assembled for
using information in the notes section. So if available, we use that,
otherwise we default to the old 'unknown' behaviour.
With the changes above code, a mode changing 'bx lr' assembled for armv4 with
the option --fix-v4bx will result in an object file that is recognized by bfd
as one for the armv4 architecture. The disassembler now disassembles this
encoding as a BX even for Armv4 architectures, but warns the user when
disassembling for Armv4 that this instruction is only valid from Armv4T
onwards.
Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and
define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by
-march=armv8-r+crc are disassembled correctly.
Patch up some of the tests cases, see a brief explanation for each below.
inst.d:
This test checks the assembly & disassembly of basic instructions in armv3m. I
changed the expected behaviour for teqp, cmnp cmpp and testp instructions to
properly print p when disassembling, whereas before, in the 'unknown' case it
would disassemble these as UNPREDICTABLE as they were changed in later
architectures.
nops.d:
Was missing an -march, added one to make sure we were testing the right
behavior of NOP<c> instructions.
unpredictable.d:
Was missing an -march, added armv6 as that reproduced the behaviour being
tested.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
ELF linker messages
This fixes a number of cases where we capitalized error messages or
printed a full-stop, and corrects "Dwarf" to "DWARF".
bfd/
* dwarf2.c, * elf-attrs.c, * elf-eh-frame.c, * elf.c, * elf32-gen.c,
* elflink.c: Standardize error/warning messages. Replace use of
linker callback einfo with _bfd_error_handler when possible.
ld/
* testsuite/ld-elf/indirect.exp,
* testsuite/ld-elf/pr22649-2ab-mips.msg,
* testsuite/ld-elf/pr22649-2cd-mips.msg,
* testsuite/ld-elf/pr22649.msg,
* testsuite/ld-elf/tls_common.exp,
* testsuite/ld-elfcomm/elfcomm.exp,
* testsuite/ld-arm/attr-merge-incompatible.d,
* testsuite/ld-tic6x/attr-compatibility-gnu-other.d,
* testsuite/ld-tic6x/attr-compatibility-other-gnu.d,
* testsuite/ld-tic6x/attr-compatibility-other-other.d,
* testsuite/ld-i386/warn1.d: Update expected error/warning messages.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
2009-11-02 Paul Brook <paul@codesourcery.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
* ld-arm/attr-merge-vfp-1.d: New test.
* ld-arm/attr-merge-vfp-1r.d: New test.
* ld-arm/attr-merge-vfp-2.d: New test.
* ld-arm/attr-merge-vfp-2r.d: New test.
* ld-arm/attr-merge-vfp-3.d: New test.
* ld-arm/attr-merge-vfp-3r.d: New test.
* ld-arm/attr-merge-vfp-4.d: New test.
* ld-arm/attr-merge-vfp-4r.d: New test.
* ld-arm/attr-merge-vfp-5.d: New test.
* ld-arm/attr-merge-vfp-5r.d: New test.
* ld-arm/attr-merge-vfp-2.s: New test.
* ld-arm/attr-merge-vfp-3.s: New test.
* ld-arm/attr-merge-vfp-3-d16.s: New test.
* ld-arm/attr-merge-vfp-4.s: New test.
* ld-arm/attr-merge-vfp-4-d16.s: New test.
gas/
* doc/c-arm.texi: Document new -mfpu options.
* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
fpu_vfp_ext_fma): New.
(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
(insns): Move double precision load/store. Split out double
precision VFPv3 instrucitons. Add VFPv4 instructions.
(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
(aeabi_set_public_attributes): Set VFPv4 variants
gas/testsuite/
* gas/arm/attr-mfpu-vfpv4.d: New test.
* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
* gas/arm/neon-fma-cov.d: New test.
* gas/arm/neon-fma-cov.s: New test.
* gas/arm/vfp-fma-inc.s: New test.
* gas/arm/vfp-fma-arm.d: New test.
* gas/arm/vfp-fma-arm.s: New test.
* gas/arm/vfp-fma-thumb.d: New test.
* gas/arm/vfp-fma-thumb.s: New test.
* gas/arm/vfma1.d: New test.
* gas/arm/vfma1.s: New test.
* gas/arm/vfpv3xd.d: New test.
* gas/arm/vfpv3xd.s: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
FPU_ARCH_NEON_VFP_V4): Define.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.
bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
attributes.
opcodes/
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
Add VFPv4 instructions.
bfd:
* bfd-in.h (bfd_elf32_arm_set_target_relocs): Add new parameter.
* bfd-in2.h: Regenerate.
* elf32-arm.c (struct elf_arm_obj_tdata): Add field
no_wchar_size_warning.
(bfd_elf32_arm_set_target_relocs): Add new parameter
no_wchar_warn.
(elf32_arm_merge_eabi_attributes): Give a warning, not an error,
for conflicting wchar_t attributes. Do not warn if
--no-wchar-size-warning. Make diagnostic text more specific.
ld:
* ld.texinfo (--no-wchar-size-warning): Document new ARM option.
* emultempl/armelf.em (no_wchar_size_warning): New.
(arm_elf_create_output_section_statements): Pass
no_wchar_size_warning to arm_elf_create_output_section_statements.
(OPTION_NO_WCHAR_SIZE_WARNING): New.
(PARSE_AND_LIST_LONGOPTS): Add no-wchar-size-warning.
(PARSE_AND_LIST_OPTIONS): List --no-wchar-size-warning.
(PARSE_AND_LIST_ARGS_CASES): Handle --no-wchar-size-warning.
ld/testsuite:
* ld-arm/attr-merge-wchar-0.s,ld-arm/attr-merge-wchar-2.s,
ld-arm/attr-merge-wchar-4.s, ld-arm/attr-merge-wchar-00-nowarn.d,
ld-arm/attr-merge-wchar-00.d, ld-arm/attr-merge-wchar-02-nowarn.d,
ld-arm/attr-merge-wchar-02.d, ld-arm/attr-merge-wchar-04-nowarn.d,
ld-arm/attr-merge-wchar-04.d, ld-arm/attr-merge-wchar-20-nowarn.d,
ld-arm/attr-merge-wchar-20.d, ld-arm/attr-merge-wchar-22-nowarn.d,
ld-arm/attr-merge-wchar-22.d, ld-arm/attr-merge-wchar-24-nowarn.d,
ld-arm/attr-merge-wchar-24.d, ld-arm/attr-merge-wchar-40-nowarn.d,
ld-arm/attr-merge-wchar-40.d, ld-arm/attr-merge-wchar-42-nowarn.d,
ld-arm/attr-merge-wchar-42.d, ld-arm/attr-merge-wchar-44-nowarn.d,
ld-arm/attr-merge-wchar-44.d: New.
* ld-arm/arm-elf.exp: Run new tests.
bfd:
* bfd-in.h (bfd_elf32_arm_set_target_relocs): Add new parameter.
* bfd-in2.h: Regenerate.
* elf32-arm.c (struct elf_arm_obj_tdata): Add field
no_wchar_size_warning.
(bfd_elf32_arm_set_target_relocs): Add new parameter
no_wchar_warn.
(elf32_arm_merge_eabi_attributes): Give a warning, not an error,
for conflicting wchar_t attributes. Do not warn if
--no-wchar-size-warning. Make diagnostic text more specific.
ld:
* ld.texinfo (--no-wchar-size-warning): Document new ARM option.
* emultempl/armelf.em (no_wchar_size_warning): New.
(arm_elf_create_output_section_statements): Pass
no_wchar_size_warning to arm_elf_create_output_section_statements.
(OPTION_NO_WCHAR_SIZE_WARNING): New.
(PARSE_AND_LIST_LONGOPTS): Add no-wchar-size-warning.
(PARSE_AND_LIST_OPTIONS): List --no-wchar-size-warning.
(PARSE_AND_LIST_ARGS_CASES): Handle --no-wchar-size-warning.
ld/testsuite:
* ld-arm/attr-merge-wchar-0.s,ld-arm/attr-merge-wchar-2.s,
ld-arm/attr-merge-wchar-4.s, ld-arm/attr-merge-wchar-00-nowarn.d,
ld-arm/attr-merge-wchar-00.d, ld-arm/attr-merge-wchar-02-nowarn.d,
ld-arm/attr-merge-wchar-02.d, ld-arm/attr-merge-wchar-04-nowarn.d,
ld-arm/attr-merge-wchar-04.d, ld-arm/attr-merge-wchar-20-nowarn.d,
ld-arm/attr-merge-wchar-20.d, ld-arm/attr-merge-wchar-22-nowarn.d,
ld-arm/attr-merge-wchar-22.d, ld-arm/attr-merge-wchar-24-nowarn.d,
ld-arm/attr-merge-wchar-24.d, ld-arm/attr-merge-wchar-40-nowarn.d,
ld-arm/attr-merge-wchar-40.d, ld-arm/attr-merge-wchar-42-nowarn.d,
ld-arm/attr-merge-wchar-42.d, ld-arm/attr-merge-wchar-44-nowarn.d,
ld-arm/attr-merge-wchar-44.d: New.
* ld-arm/arm-elf.exp: Run new tests.
bfd:
* bfd-in.h (bfd_elf32_arm_set_target_relocs): Add new parameter.
* bfd-in2.h: Regenerate.
* elf32-arm.c (struct elf_arm_obj_tdata): Add field
no_wchar_size_warning.
(bfd_elf32_arm_set_target_relocs): Add new parameter
no_wchar_warn.
(elf32_arm_merge_eabi_attributes): Give a warning, not an error,
for conflicting wchar_t attributes. Do not warn if
--no-wchar-size-warning. Make diagnostic text more specific.
ld:
* ld.texinfo (--no-wchar-size-warning): Document new ARM option.
* emultempl/armelf.em (no_wchar_size_warning): New.
(arm_elf_create_output_section_statements): Pass
no_wchar_size_warning to arm_elf_create_output_section_statements.
(OPTION_NO_WCHAR_SIZE_WARNING): New.
(PARSE_AND_LIST_LONGOPTS): Add no-wchar-size-warning.
(PARSE_AND_LIST_OPTIONS): List --no-wchar-size-warning.
(PARSE_AND_LIST_ARGS_CASES): Handle --no-wchar-size-warning.
ld/testsuite:
* ld-arm/attr-merge-wchar-0.s,ld-arm/attr-merge-wchar-2.s,
ld-arm/attr-merge-wchar-4.s, ld-arm/attr-merge-wchar-00-nowarn.d,
ld-arm/attr-merge-wchar-00.d, ld-arm/attr-merge-wchar-02-nowarn.d,
ld-arm/attr-merge-wchar-02.d, ld-arm/attr-merge-wchar-04-nowarn.d,
ld-arm/attr-merge-wchar-04.d, ld-arm/attr-merge-wchar-20-nowarn.d,
ld-arm/attr-merge-wchar-20.d, ld-arm/attr-merge-wchar-22-nowarn.d,
ld-arm/attr-merge-wchar-22.d, ld-arm/attr-merge-wchar-24-nowarn.d,
ld-arm/attr-merge-wchar-24.d, ld-arm/attr-merge-wchar-40-nowarn.d,
ld-arm/attr-merge-wchar-40.d, ld-arm/attr-merge-wchar-42-nowarn.d,
ld-arm/attr-merge-wchar-42.d, ld-arm/attr-merge-wchar-44-nowarn.d,
ld-arm/attr-merge-wchar-44.d: New.
* ld-arm/arm-elf.exp: Run new tests.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
ld/
* emultempl/armelf.em (fix_cortex_a8): New.
(arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
(arm_elf_create_output_section_statements): Add fix_cortex_a8 to
bfd_elf32_arm_set_target_relocs.
(OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
(PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
* ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.
bfd/
* elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
New macros.
(elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
(elf32_arm_stub_a8_veneer_blx): New stub sequences.
(elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
(elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
(a8_erratum_fix, a8_erratum_reloc): New structs.
(elf32_arm_link_hash_table): Add a8_erratum_fixes,
num_a8_erratum_fixes, fix_cortex_a8 fields.
(elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
(elf32_arm_add_stub): Split into two parts, creating...
(elf32_arm_create_or_find_stub_sec): New function.
(elf32_arm_final_link_relocate): Add forward declaration.
(arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
relocations, multiple relocations per stub.
(find_stub_size_and_template): New (using parts of
arm_size_one_stub).
(arm_size_one_stub): Use find_stub_size_and_template.
(a8_reloc_compare): New.
(find_thumb_glue): Add forward declaration.
(cortex_a8_erratum_scan): New.
(elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
(bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
(arm_map_one_stub): Add THUMB32_TYPE support.
(a8_branch_to_stub_data): New.
(make_branch_to_a8_stub): New.
(elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
* bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
(bfd_elf32_arm_set_target_relocs): Add argument for controlling
Cortex-A8 erratum workaround.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-arm/cortex-a8-arm-target.s: New.
* ld-arm/cortex-a8-thumb-target.s: New.
* ld-arm/cortex-a8-fix-b-rel.s: New.
* ld-arm/cortex-a8-fix-b-rel-arm.d: New.
* ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-b.s: New.
* ld-arm/cortex-a8-fix-b.d: New.
* ld-arm/cortex-a8-fix-bl-rel.s: New.
* ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
* ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bl.s: New.
* ld-arm/cortex-a8-fix-bl.d: New.
* ld-arm/cortex-a8-fix-bcc-rel.s: New.
* ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-bcc.s: New.
* ld-arm/cortex-a8-fix-bcc.d: New.
* ld-arm/cortex-a8-fix-blx-rel.s: New.
* ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
* ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
* ld-arm/cortex-a8-fix-blx.s: New.
* ld-arm/cortex-a8-fix-blx.d: New.
* ld-arm/arm-elf.exp: Add new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* elf32-arm.c (THM2_MAX_FWD_BRANCH_OFFSET): Define.
(THM2_MAX_BWD_BRANCH_OFFSET): Define.
(ARM_MAX_FWD_BRANCH_OFFSET): Define.
(ARM_MAX_BWD_BRANCH_OFFSET): Define.
(THM_MAX_FWD_BRANCH_OFFSET): Define.
(THM_MAX_BWD_BRANCH_OFFSET): Define.
(arm_long_branch_stub): Define.
(arm_pic_long_branch_stub): Define.
(arm_thumb_v4t_long_branch_stub): Define.
(arm_thumb_thumb_long_branch_stub): Define.
(arm_thumb_arm_v4t_long_branch_stub): Define.
(STUB_SUFFIX): Define.
(elf32_arm_stub_type): Define.
(elf32_arm_stub_hash_entry): Define.
(elf32_arm_link_hash_entry): Add stub_cache field.
(arm_stub_hash_lookup): Define.
(elf32_arm_link_hash_table): Add stub_hash_table, stub_bfd,
add_stub_section, layout_sections_again, stub_group, bfd_count,
top_index, input_list fields.
(elf32_arm_link_hash_newfunc): Init new field.
(stub_hash_newfunc): New function.
(elf32_arm_link_hash_table_create): Init stub_hash_table.
(elf32_arm_hash_table_free): New function.
(arm_type_of_stub): New function.
(elf32_arm_stub_name): New function.
(elf32_arm_get_stub_entry): New function.
(elf32_arm_stub_add_mapping_symbol): New function.
(elf32_arm_add_stub): New function.
(arm_build_one_stub): New function.
(arm_size_one_stub): New function.
(elf32_arm_setup_section_lists): New function.
(elf32_arm_next_input_section): New function.
(group_sections): New function.
(elf32_arm_size_stubs): New function.
(elf32_arm_build_stubs): New function.
(bfd_elf32_arm_add_glue_sections_to_bfd): Skip stub sections.
(bfd_elf32_arm_process_before_allocation): No longer handle
R_ARM_CALL and R_ARM_THM_CALL.
(using_thumb_only): New function.
(elf32_arm_final_link_relocate): Redirect calls to stub if range
exceeds encoding capabilities.
(bfd_elf32_bfd_link_hash_table_free): Define.
* bfd-in.h (R_ARM_max): Fix value to 130.
(elf32_arm_setup_section_lists): Protype.
(elf32_arm_next_input_section): Protype.
(elf32_arm_size_stubs): Protype.
(elf32_arm_build_stubs): Protype.
ld/
* emultempl/armelf.em (build_section_lists): New function.
(stub_file): Define.
(need_laying_out): Define.
(group_size): Define.
(hook_stub_info): Define.
(hook_in_stub): New function.
(elf32_arm_add_stub_section): New function.
(gldarm_layout_sections_again): New function.
(gld${EMULATION_NAME}_finish): Replace arm_elf_finish(). Generate
stubs for long calls if needed.
(arm_elf_create_output_section_statements): create stub_file bfd.
(arm_for_each_input_file_wrapper): New function.
(arm_lang_for_each_input_file): New function.
(lang_for_each_input_file): Define.
(PARSE_AND_LIST_PROLOGUE): Add option token OPTION_STUBGROUP_SIZE.
(PARSE_AND_LIST_LONGOPTS): Add option stub-group-size.
(PARSE_AND_LIST_OPTIONS): Add option stub-group-size.
(PARSE_AND_LIST_ARGS_CASES): Add OPTION_STUBGROUP_SIZE case.
(LDEMUL_FINISH): Update to gld${EMULATION_NAME}_finish.
* ld/lang.c (print_input_statement): Skip if bfd has
BFD_LINKER_CREATED.
ld/testsuite
* ld-arm/arm-elf.exp (armelftests): Add farcall-arm-arm,
farcall-arm-arm-pic-veneer, farcall-arm-arm-be8 farcall-arm-thumb,
farcall-arm-thumb-blx, farcall-arm-thumb-pic-veneer,
farcall-arm-thumb-blx-pic-veneer, farcall-thumb-thumb,
farcall-thumb-thumb-pic-veneer, farcall-thumb-thumb-blx,
farcall-thumb-thumb-m, farcall-thumb-thumb-m-pic-veneer,
farcall-thumb-thumb-blx-pic-veneer, farcall-thumb-arm,
farcall-thumb-arm-pic-veneer, farcall-thumb-arm-blx,
farcall-thumb-arm-blx-pic-veneer.
Change thumb2-bl-as-thumb1-bad, thumb2-bl-bad.
* ld-arm/thumb2-bl-as-thumb1-bad.d: Reflects farcall stub
generation.
* ld-arm/thumb2-bl-bad.d: Likewise.
* ld-arm/thumb2-bl-as-thumb1-bad.s: Update comments.
* ld-arm/thumb2-bl-bad.s: Likewise.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* elf32-arm.c (THM2_MAX_FWD_BRANCH_OFFSET): Define.
(THM2_MAX_BWD_BRANCH_OFFSET): Define.
(ARM_MAX_FWD_BRANCH_OFFSET): Define.
(ARM_MAX_BWD_BRANCH_OFFSET): Define.
(THM_MAX_FWD_BRANCH_OFFSET): Define.
(THM_MAX_BWD_BRANCH_OFFSET): Define.
(arm_long_branch_stub): Define.
(arm_pic_long_branch_stub): Define.
(arm_thumb_v4t_long_branch_stub): Define.
(arm_thumb_thumb_long_branch_stub): Define.
(arm_thumb_arm_v4t_long_branch_stub): Define.
(STUB_SUFFIX): Define.
(elf32_arm_stub_type): Define.
(elf32_arm_stub_hash_entry): Define.
(elf32_arm_link_hash_entry): Add stub_cache field.
(arm_stub_hash_lookup): Define.
(elf32_arm_link_hash_table): Add stub_hash_table, stub_bfd,
add_stub_section, layout_sections_again, stub_group, bfd_count,
top_index, input_list fields.
(elf32_arm_link_hash_newfunc): Init new field.
(stub_hash_newfunc): New function.
(elf32_arm_link_hash_table_create): Init stub_hash_table.
(elf32_arm_hash_table_free): New function.
(arm_type_of_stub): New function.
(elf32_arm_stub_name): New function.
(elf32_arm_get_stub_entry): New function.
(elf32_arm_stub_add_mapping_symbol): New function.
(elf32_arm_add_stub): New function.
(arm_build_one_stub): New function.
(arm_size_one_stub): New function.
(elf32_arm_setup_section_lists): New function.
(elf32_arm_next_input_section): New function.
(group_sections): New function.
(elf32_arm_size_stubs): New function.
(elf32_arm_build_stubs): New function.
(bfd_elf32_arm_add_glue_sections_to_bfd): Skip stub sections.
(bfd_elf32_arm_process_before_allocation): No longer handle
R_ARM_CALL and R_ARM_THM_CALL.
(using_thumb_only): New function.
(elf32_arm_final_link_relocate): Redirect calls to stub if range
exceeds encoding capabilities.
(bfd_elf32_bfd_link_hash_table_free): Define.
* bfd-in.h (R_ARM_max): Fix value to 130.
(elf32_arm_setup_section_lists): Protype.
(elf32_arm_next_input_section): Protype.
(elf32_arm_size_stubs): Protype.
(elf32_arm_build_stubs): Protype.
ld/
* emultempl/armelf.em (build_section_lists): New function.
(stub_file): Define.
(need_laying_out): Define.
(group_size): Define.
(hook_stub_info): Define.
(hook_in_stub): New function.
(elf32_arm_add_stub_section): New function.
(gldarm_layout_sections_again): New function.
(gld${EMULATION_NAME}_finish): Replace arm_elf_finish(). Generate
stubs for long calls if needed.
(arm_elf_create_output_section_statements): create stub_file bfd.
(arm_for_each_input_file_wrapper): New function.
(arm_lang_for_each_input_file): New function.
(lang_for_each_input_file): Define.
(PARSE_AND_LIST_PROLOGUE): Add option token OPTION_STUBGROUP_SIZE.
(PARSE_AND_LIST_LONGOPTS): Add option stub-group-size.
(PARSE_AND_LIST_OPTIONS): Add option stub-group-size.
(PARSE_AND_LIST_ARGS_CASES): Add OPTION_STUBGROUP_SIZE case.
(LDEMUL_FINISH): Update to gld${EMULATION_NAME}_finish.
* ld/lang.c (print_input_statement): Skip if bfd has
BFD_LINKER_CREATED.
ld/testsuite
* ld-arm/arm-elf.exp (armelftests): Add farcall-arm-arm,
farcall-arm-arm-pic-veneer, farcall-arm-arm-be8 farcall-arm-thumb,
farcall-arm-thumb-blx, farcall-arm-thumb-pic-veneer,
farcall-arm-thumb-blx-pic-veneer, farcall-thumb-thumb,
farcall-thumb-thumb-pic-veneer, farcall-thumb-thumb-blx,
farcall-thumb-thumb-m, farcall-thumb-thumb-m-pic-veneer,
farcall-thumb-thumb-blx-pic-veneer, farcall-thumb-arm,
farcall-thumb-arm-pic-veneer, farcall-thumb-arm-blx,
farcall-thumb-arm-blx-pic-veneer.
Change thumb2-bl-as-thumb1-bad, thumb2-bl-bad.
* ld-arm/thumb2-bl-as-thumb1-bad.d: Reflects farcall stub
generation.
* ld-arm/thumb2-bl-bad.d: Likewise.
* ld-arm/thumb2-bl-as-thumb1-bad.s: Update comments.
* ld-arm/thumb2-bl-bad.s: Likewise.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
* include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}
to R_ARM_LDC_SB_G{0,1,2} respectively.
bfd/
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
gas/
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
ld/testsuite/
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
* include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}
to R_ARM_LDC_SB_G{0,1,2} respectively.
bfd/
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
gas/
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
ld/testsuite/
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
ARM and AArch64 messages
More standarization of error/warning messages. The ARM backend has
some multi-line error messages, which don't fit particularly well with
the GNU coding standard insistence that error messages shouldn't be
capitalized or have a full-stop. I've replaced the line breaks with
semicolons.
So for instance the following
system/path/to/ld: myobject.o: invalid special symbol `foo'.
system/path/to/ld: It must be a global or weak function symbol.
becomes
system/path/to/ld: myobject.o: invalid special symbol `foo'; it must be a global or weak function symbol
bfd/
* elf32-arm.c, * elfnn-aarch64.c: Standardize error/warning messages.
ld/
* testsuite/ld-aarch64/reloc-overflow-bad.d,
* testsuite/ld-arm/attr-merge-9.out,
* testsuite/ld-arm/attr-merge-arch-2.d,
* testsuite/ld-arm/attr-merge-unknown-1.d,
* testsuite/ld-arm/attr-merge-unknown-2.d,
* testsuite/ld-arm/attr-merge-unknown-2r.d,
* testsuite/ld-arm/attr-merge-unknown-3.d,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-no-output.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/group-relocs-alu-bad-2.d,
* testsuite/ld-arm/group-relocs-alu-bad.d,
* testsuite/ld-arm/group-relocs-ldc-bad-2.d,
* testsuite/ld-arm/group-relocs-ldc-bad.d,
* testsuite/ld-arm/group-relocs-ldr-bad-2.d,
* testsuite/ld-arm/group-relocs-ldr-bad.d,
* testsuite/ld-arm/group-relocs-ldrs-bad-2.d,
* testsuite/ld-arm/group-relocs-ldrs-bad.d,
* testsuite/ld-arm/stm32l4xx-cannot-fix-far-ldm.d: Update.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
readelf ngettext fixes
This patch is a first pass at fixing readelf message pluralization.
I've deliberately not fixed the "out of memory" errors since it's very
unlikely that they will ever be complaining about not being able to
allocate for a single entry, and a few others where the size is very
unlikely to be 1 byte.
Then there are messages like this one:
"Out of %lu items there are %zu bucket clashes (longest of %zu entries).\n"
I suppose this could be split into three parts, "Of %lu items ",
"there are %zu bucket clashes ", and "(longest of %zu entries).\n",
each part being printed separately, but that might not be ideal for
sentence construction in other languages. For now I'm punting on this
one.
Changes to readelf output require lots of testsuite adjustment..
binutils/
* dwarf.c (read_uleb128): Properly pluralize messages.
(display_debug_lines_raw, display_debug_loc): Likewise.
(display_debug_names, process_cu_tu_index): Likewise.
* od-macho.c (dump_code_signature_superblob): Likewise.
* readelf.c (process_program_headers): Likewise.
(process_section_header, process_relocs): Likewise.
(hppa_process_unwind, arm_process_unwind): Likewise.
(process_dynamic_section, process_version_sections): Likewise.
(process_symbol_table, process_syminfo): Likewise.
(apply_relocations, process_mips_specific): Likewise.
(process_gnu_liblist, process_notes_at): Likewise.
(process_archive): Likewise.
* testsuite/binutils-all/dw2-1.W,
* testsuite/binutils-all/dw2-3.W,
* testsuite/binutils-all/dw2-3gabi.W,
* testsuite/binutils-all/dw5.S,
* testsuite/binutils-all/dw5.W,
* testsuite/binutils-all/i386/compressed-1a.d,
* testsuite/binutils-all/libdw2-compressedgabi.out,
* testsuite/binutils-all/objdump.W,
* testsuite/binutils-all/readelf.r,
* testsuite/binutils-all/readelf.r-64,
* testsuite/binutils-all/x86-64/compressed-1a.d: Update
for pluralization fixes.
gas/
* testsuite/gas/arm/got_prel.d,
* testsuite/gas/elf/dwarf2-1.d,
* testsuite/gas/elf/dwarf2-2.d,
* testsuite/gas/elf/dwarf2-3.d,
* testsuite/gas/elf/dwarf2-5.d,
* testsuite/gas/elf/dwarf2-6.d,
* testsuite/gas/i386/debug1.d,
* testsuite/gas/i386/dw2-compress-1.d,
* testsuite/gas/i386/dw2-compress-3a.d,
* testsuite/gas/i386/dw2-compress-3b.d,
* testsuite/gas/i386/dw2-compressed-1.d,
* testsuite/gas/i386/dw2-compressed-3a.d,
* testsuite/gas/i386/dw2-compressed-3b.d,
* testsuite/gas/i386/ilp32/x86-64-localpic.d,
* testsuite/gas/i386/localpic.d,
* testsuite/gas/i386/x86-64-localpic.d,
* testsuite/gas/ia64/pr13167.d,
* testsuite/gas/mips/loc-swap-2.d,
* testsuite/gas/mips/loc-swap.d,
* testsuite/gas/mips/micromips@loc-swap-2.d,
* testsuite/gas/mips/micromips@loc-swap.d,
* testsuite/gas/mips/mips16-dwarf2-n32.d,
* testsuite/gas/mips/mips16-dwarf2.d,
* testsuite/gas/mips/mips16@loc-swap-2.d,
* testsuite/gas/mips/mips16@loc-swap.d,
* testsuite/gas/mips/mips16e@loc-swap.d,
* testsuite/gas/mmix/bspec-1.d,
* testsuite/gas/mmix/bspec-2.d,
* testsuite/gas/tic6x/unwind-1.d,
* testsuite/gas/tic6x/unwind-2.d,
* testsuite/gas/tic6x/unwind-3.d: Update for pluralization
fixes.
ld/
* testsuite/ld-aarch64/ifunc-13.d,
* testsuite/ld-aarch64/ifunc-15.d,
* testsuite/ld-aarch64/ifunc-20.d,
* testsuite/ld-alpha/tlsbin.rd,
* testsuite/ld-alpha/tlspic.rd,
* testsuite/ld-arm/ifunc-3.rd,
* testsuite/ld-arm/ifunc-9.rd,
* testsuite/ld-arm/unwind-mix.d,
* testsuite/ld-arm/unwind-rel.d,
* testsuite/ld-cris/hiddef1.d,
* testsuite/ld-cris/libdso-13.d,
* testsuite/ld-cris/libdso-2.d,
* testsuite/ld-cris/pr16044.d,
* testsuite/ld-cris/tls-local-63.d,
* testsuite/ld-cris/tls-local-64.d,
* testsuite/ld-cris/tls-und-38.d,
* testsuite/ld-cris/tls-und-42.d,
* testsuite/ld-cris/tls-und-46.d,
* testsuite/ld-cris/tls-und-50.d,
* testsuite/ld-cris/weakref3.d,
* testsuite/ld-cris/weakref4.d,
* testsuite/ld-elf/comm-data2r.rd,
* testsuite/ld-elf/discard1.d,
* testsuite/ld-elf/discard2.d,
* testsuite/ld-elf/pr19539.d,
* testsuite/ld-elf/pr22374-1.r,
* testsuite/ld-elf/pr22374-2.r,
* testsuite/ld-i386/combreloc.d,
* testsuite/ld-i386/emit-relocs-nacl.rd,
* testsuite/ld-i386/emit-relocs.rd,
* testsuite/ld-i386/pr13302.d,
* testsuite/ld-i386/pr17709-nacl.rd,
* testsuite/ld-i386/pr17709.rd,
* testsuite/ld-i386/pr19539.d,
* testsuite/ld-i386/pr19615.d,
* testsuite/ld-i386/pr19636-1a.d,
* testsuite/ld-i386/pr19636-1e.d,
* testsuite/ld-i386/pr19636-1f.d,
* testsuite/ld-i386/pr19636-2a.d,
* testsuite/ld-i386/pr19636-2b.d,
* testsuite/ld-i386/pr19636-2d-nacl.d,
* testsuite/ld-i386/pr19636-2e-nacl.d,
* testsuite/ld-i386/pr19636-3a.d,
* testsuite/ld-i386/pr19636-3d.d,
* testsuite/ld-i386/pr19636-3e.d,
* testsuite/ld-i386/pr19636-4a.d,
* testsuite/ld-i386/pr19645.d,
* testsuite/ld-i386/pr19827-nacl.rd,
* testsuite/ld-i386/pr19827.rd,
* testsuite/ld-i386/pr20253-4a.d,
* testsuite/ld-i386/pr20253-4b.d,
* testsuite/ld-i386/pr20253-5.d,
* testsuite/ld-i386/tlsbin-nacl.rd,
* testsuite/ld-i386/tlsbin.rd,
* testsuite/ld-i386/tlspic-nacl.rd,
* testsuite/ld-i386/tlspic.rd,
* testsuite/ld-i386/undefweakb.d,
* testsuite/ld-ia64/tlsbin.rd,
* testsuite/ld-ia64/tlspic.rd,
* testsuite/ld-ifunc/ifunc-13-i386.d,
* testsuite/ld-ifunc/ifunc-13-x86-64.d,
* testsuite/ld-ifunc/ifunc-15-i386.d,
* testsuite/ld-ifunc/ifunc-15-x86-64.d,
* testsuite/ld-ifunc/ifunc-20-i386.d,
* testsuite/ld-ifunc/ifunc-20-x86-64.d,
* testsuite/ld-ifunc/ifunc-23a-x86.d,
* testsuite/ld-ifunc/ifunc-23b-x86.d,
* testsuite/ld-ifunc/ifunc-23c-x86.d,
* testsuite/ld-ifunc/ifunc-24a-x86.d,
* testsuite/ld-ifunc/ifunc-24b-x86.d,
* testsuite/ld-ifunc/ifunc-24c-x86.d,
* testsuite/ld-ifunc/ifunc-25a-x86.d,
* testsuite/ld-ifunc/ifunc-25b-x86.d,
* testsuite/ld-ifunc/ifunc-25c-x86.d,
* testsuite/ld-m68k/got-1.d,
* testsuite/ld-mips-elf/vxworks1.rd,
* testsuite/ld-powerpc/ambiguousv1.d,
* testsuite/ld-powerpc/ambiguousv1b.d,
* testsuite/ld-powerpc/ambiguousv2.d,
* testsuite/ld-powerpc/ambiguousv2b.d,
* testsuite/ld-powerpc/tlsexe.r,
* testsuite/ld-powerpc/tlsexe32.r,
* testsuite/ld-powerpc/tlsexetoc.r,
* testsuite/ld-powerpc/tlsso.r,
* testsuite/ld-powerpc/tlsso32.r,
* testsuite/ld-powerpc/tlstocso.r,
* testsuite/ld-powerpc/vle-multiseg-1.d,
* testsuite/ld-powerpc/vle-multiseg-2.d,
* testsuite/ld-powerpc/vle-multiseg-3.d,
* testsuite/ld-s390/tlsbin.rd,
* testsuite/ld-s390/tlsbin_64.rd,
* testsuite/ld-s390/tlspic.rd,
* testsuite/ld-s390/tlspic_64.rd,
* testsuite/ld-sh/ld-r-1.d,
* testsuite/ld-sh/sh64/gotplt.d,
* testsuite/ld-sh/shared-1.d,
* testsuite/ld-sh/tlsbin-2.d,
* testsuite/ld-sh/tlspic-2.d,
* testsuite/ld-sparc/gotop32.rd,
* testsuite/ld-sparc/gotop64.rd,
* testsuite/ld-sparc/tlssunpic32.rd,
* testsuite/ld-sparc/tlssunpic64.rd,
* testsuite/ld-sparc/vxworks1-lib.rd,
* testsuite/ld-tic6x/shlib-app-1.rd,
* testsuite/ld-tic6x/shlib-app-1b.rd,
* testsuite/ld-tic6x/shlib-app-1r.rd,
* testsuite/ld-tic6x/shlib-app-1rb.rd,
* testsuite/ld-tic6x/shlib-noindex.rd,
* testsuite/ld-vax-elf/export-class-data.rd,
* testsuite/ld-x86-64/pr13082-1a.d,
* testsuite/ld-x86-64/pr13082-1b.d,
* testsuite/ld-x86-64/pr13082-2a.d,
* testsuite/ld-x86-64/pr13082-2b.d,
* testsuite/ld-x86-64/pr13082-3a.d,
* testsuite/ld-x86-64/pr13082-3c.d,
* testsuite/ld-x86-64/pr13082-4a.d,
* testsuite/ld-x86-64/pr13082-5a.d,
* testsuite/ld-x86-64/pr13082-5b.d,
* testsuite/ld-x86-64/pr13082-6a.d,
* testsuite/ld-x86-64/pr13082-6b.d,
* testsuite/ld-x86-64/pr17709-nacl.rd,
* testsuite/ld-x86-64/pr17709.rd,
* testsuite/ld-x86-64/pr19539a.d,
* testsuite/ld-x86-64/pr19539b.d,
* testsuite/ld-x86-64/pr19615.d,
* testsuite/ld-x86-64/pr19636-1a.d,
* testsuite/ld-x86-64/pr19636-1d.d,
* testsuite/ld-x86-64/pr19636-1e.d,
* testsuite/ld-x86-64/pr19636-2a.d,
* testsuite/ld-x86-64/pr19636-2e.d,
* testsuite/ld-x86-64/pr19636-2f.d,
* testsuite/ld-x86-64/pr19636-3a.d,
* testsuite/ld-x86-64/pr19645.d,
* testsuite/ld-x86-64/pr19807-2b.d,
* testsuite/ld-x86-64/pr19807-2d.d,
* testsuite/ld-x86-64/pr19827-nacl.rd,
* testsuite/ld-x86-64/pr19827.rd,
* testsuite/ld-x86-64/pr20253-4a.d,
* testsuite/ld-x86-64/pr20253-4b.d,
* testsuite/ld-x86-64/pr20253-4d.d,
* testsuite/ld-x86-64/pr20253-4e.d,
* testsuite/ld-x86-64/pr20253-5a.d,
* testsuite/ld-x86-64/pr20253-5b.d,
* testsuite/ld-x86-64/tlsbin-nacl.rd,
* testsuite/ld-x86-64/tlsbin.rd,
* testsuite/ld-x86-64/tlspic-nacl.rd,
* testsuite/ld-x86-64/tlspic.rd,
* testsuite/ld-x86-64/tlspic2-nacl.rd: Update for
pluralization fixes.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
include/elf/
* arm.h (R_ARM_IRELATIVE): New relocation.
bfd/
* reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation.
* bfd-in2.h: Regenerate.
* elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition
to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE
entry.
(elf32_arm_howto_from_type): Update accordingly.
(elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE.
(elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3.
(arm_plt_info): New structure, split out from elf32_arm_link_hash_entry
with an extra noncall_refcount field.
(arm_local_iplt_info): New structure.
(elf_arm_obj_tdata): Add local_iplt.
(elf32_arm_local_iplt): New accessor macro.
(elf32_arm_link_hash_entry): Replace plt_thumb_refcount,
plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info.
Change tls_type to a bitfield and add is_iplt.
(elf32_arm_link_hash_newfunc): Update accordingly.
(elf32_arm_allocate_local_sym_info): New function.
(elf32_arm_create_local_iplt): Likewise.
(elf32_arm_get_plt_info): Likewise.
(elf32_arm_plt_needs_thumb_stub_p): Likewise.
(elf32_arm_get_local_dynreloc_list): Likewise.
(create_ifunc_sections): Likewise.
(elf32_arm_copy_indirect_symbol): Update after the changes to
elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set.
(arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info
to get PLT information. Assert that all STT_GNU_IFUNC references
are turned into PLT references.
(arm_build_one_stub): Pass the symbol type to
elf32_arm_final_link_relocate.
(elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub.
(elf32_arm_allocate_irelocs): New function.
(elf32_arm_add_dynreloc): In static objects, use .rel.iplt for
all R_ARM_IRELATIVE.
(elf32_arm_allocate_plt_entry): New function.
(elf32_arm_populate_plt_entry): Likewise.
(elf32_arm_final_link_relocate): Add an st_type parameter.
Set srelgot to null for static objects. Use separate variables
to record which st_value and st_type should be used when generating
a dynamic relocation. Use elf32_arm_get_plt_info to find the
symbol's PLT information, setting has_iplt_entry, splt,
plt_offset and gotplt_offset accordingly. Check whether
STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change
the relocation target accordingly. Broaden assert to include
.iplts. Don't set sreloc for static relocations. Assert that
we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32
and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead
of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC
symbol. Pass the symbol type to arm_type_of_stub. Conditionally
resolve GOT references to the .igot.plt entry.
(elf32_arm_relocate_section): Update the call to
elf32_arm_final_link_relocate.
(elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT
information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call
relocations in shared libraries and relocatable executables.
Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_check_relocs): Always create ifunc sections. Set isym
at the same time as setting h. Use elf32_arm_allocate_local_sym_info
to allocate local symbol information. Treat R_ARM_REL32 and
R_ARM_REL32_NOI as call relocations in shared libraries and
relocatable executables. Record PLT information for local
STT_GNU_IFUNC functions as well as global functions. Count
non-call PLT references. Use elf32_arm_get_local_dynreloc_list
to get the list of dynamic relocations for a local symbol.
(elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols.
Don't remove STT_GNU_IFUNC PLTs unless all references have been
removed. Update after the changes to elf32_arm_link_hash_entry.
(allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT
entries should live in .plt or .iplt. Check whether the .igot.plt
and .got entries can be combined. Use elf32_arm_allocate_plt_entry
to allocate .plt and .(i)got.plt entries. Detect which .got
entries will need R_ARM_IRELATIVE relocations and use
elf32_arm_allocate_irelocs to allocate them. Likewise other
non-.got dynamic relocations.
(elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt
and dynamic relocations for local STT_GNU_IFUNC symbols.
Check whether the .igot.plt and .got entries can be combined.
Detect which .got entries will need R_ARM_IRELATIVE relocations
and use elf32_arm_allocate_irelocs to allocate them. Use stashed
section pointers intead of strcmp checks. Handle iplt and igotplt.
(elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry
to fill in .plt, .got.plt and .rel(a).plt entries. Point
STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations
resolve to it.
(elf32_arm_output_plt_map_1): New function, split out from
elf32_arm_output_plt_map. Handle .iplt entries. Use
elf32_arm_plt_needs_thumb_stub_p.
(elf32_arm_output_plt_map): Call it.
(elf32_arm_output_arch_local_syms): Add mapping symbols for
local .iplt entries.
(elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols.
(elf32_arm_swap_symbol_out): Likewise.
(elf32_arm_add_symbol_hook): New function.
(elf_backend_add_symbol_hook): Define for all targets.
opcodes/
* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
gas/
* config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to
determine whether a relocation is needed.
(md_apply_fix, arm_apply_sym_value): Likewise.
ld/testsuite/
* ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd,
ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd,
ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s,
ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd,
ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd,
ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd,
ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s,
ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd,
ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd,
ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd,
ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s,
ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd,
ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd,
ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd,
ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s,
ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd,
ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd,
ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd,
ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s,
ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd,
ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd,
ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld,
ld-arm/ifunc-static.ld: New tests.
* ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d,
ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update
for new stub hashes.
* ld-arm/arm-elf.exp: Run them.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
* elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
ld: fix segfault caused by untagged stub sections
In the case of non-contiguous memory regions, a far-call stub section
must be assigned to the memory of the section it was originally emitted
for. If the stub section does not fit, the section is marked as dropped,
and removed later. To emit a useful message to the user, however, a stub
section needs to be discernible from sections originating from input
objects.
Previously [1], this distinction was made using the SEC_LINKER_CREATED
flag only in the AArch32 backend handler <arch>_add_stub_section. Other
backends that didn't set this flag on their stub sections skipped required
checks in ld/ldlang.c:size_input_section(). On AArch64, this caused the
linker to proceed into code paths that assumed output sections were set,
instead of reporting fatal errors, and ultimately led to a segmentation
fault.
However, the SEC_LINKER_CREATED flag does not solely indicate that a
section was created by the linker. Its original meaning also meant that
the section should not be handled by the generic relocation code. Reusing
this flag to identify stub sections, while it appeared to fix the issue,
introduced unintended side effects. On PowerPC, for instance, it skipped
relocations present in the stubs and interpreted them as absolute
addresses.
This patch proposes a new attribute 'veneer', indicating that a section
contains branch veneers. The attribute is set on AArch32, AArch64 and
PowerPC immediately after the creation of the stub section. Others
architectures are left unchanged, as they do not appear to support
non-contiguous memory regions (no tests were found to verify the fix).
Additionally, the diagnostic message was improved when a stub cannot be
placed in the same memory region as its referencing code.
Approved-By: Jan Beulich <jbeulich@suse.com>
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31412
[1]: abf874a, Add support for non-contiguous memory regions.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
arm: Do not insert stubs needing Arm code on Thumb-only cores.
We recently fixed a bug in libgcc
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115360)
where a symbol was missing a %function .type decoration.
This meant the linker would silently pick the wrong type of 'farcall
stub', involving Arm-mode instructions on Thumb-only CPUs.
This patch emits an error instead, and warns in some other cases, to
encourage users to add the missing '.type foo,%function' directive.
In practice: in arm_type_of_stub() we no longer try to infer which
stub to use if the destination is of unknown type and the CPU is
Thumb-only; so we won't lie to elf32_arm_size_stubs() which does not
check branch_type.
If branch_type is ST_BRANCH_TO_ARM but the CPU is Thumb-only, we now
convert it to ST_BRANCH_TO_THUMB only if the destination is of
absolute type. This is to support the case where the destination of
the branch is defined by the linker script (see thumb-b-lks-sym.s and
thumb-bl-lks-sym.s testcases for instance).
The motivating case is covered by the new farcall-missing-type
testcase, where we now emit an error message. We do not emit an error
when branch_type is ST_BRANCH_UNKNOWN and the CPU supports Arm-mode: a
lot of legacy code (e.g. newlib's crt0.S) lacks the corresponding
'.type foo, %function' directives and even a (too verbose) warning
could be perceived as a nuisance.
Existing testcases where such a warning would trigger:
arm-static-app.s (app_func, app_func2)
arm-rel32.s (foo)
arm-app.s (app_func)
rel32-reject.s () main)
fix-arm1176.s (func_to_branch_to)
but this list is not exhaustive.
For the sake of clarity, the patch replaces occurrences of
sym.st_target_internal = 0; with
sym.st_target_internal = ST_BRANCH_TO_ARM;
enum arm_st_branch_type is defined in include/elf/arm.h, and relies on
ST_BRANCH_TO_ARM==0, as sym.st_target_internal is also initialized to
0 in other target-independent parts of BFD code. (For instance,
swapping the ST_BRANCH_TO_ARM and ST_BRANCH_TO_THUMB entries in the
enum definition leads to 'interesting' results...)
Regarding the testsuite:
* new expected warning for thumb-b-lks-sym and thumb-bl-lks-sym
* new testcase farcall-missing-type to check the new error case
* attr-merge-arch-2b.s, branch-futures (and bfs-1.s) updated to avoid
a diagnostic
Tested on arm-eabi and arm-pe with no regression.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
[ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
movs r3, #:upper8_15:#foo
lsls r3, #8
adds r3, #:upper0_7:#foo
lsls r3, #8
adds r3, #:lower8_15:#foo
lsls r3, #8
adds r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
4: 2300 movs r3, #0
4: R_ARM_THM_ALU_ABS_G3_NC foo
6: 021b lsls r3, r3, #8
8: 3300 adds r3, #0
8: R_ARM_THM_ALU_ABS_G2_NC foo
a: 021b lsls r3, r3, #8
c: 3300 adds r3, #0
c: R_ARM_THM_ALU_ABS_G1_NC foo
e: 021b lsls r3, r3, #8
10: 3300 adds r3, #0
10: R_ARM_THM_ALU_ABS_G0_NC foo
* elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
[ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
movs r3, #:upper8_15:#foo
lsls r3, #8
adds r3, #:upper0_7:#foo
lsls r3, #8
adds r3, #:lower8_15:#foo
lsls r3, #8
adds r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
4: 2300 movs r3, #0
4: R_ARM_THM_ALU_ABS_G3_NC foo
6: 021b lsls r3, r3, #8
8: 3300 adds r3, #0
8: R_ARM_THM_ALU_ABS_G2_NC foo
a: 021b lsls r3, r3, #8
c: 3300 adds r3, #0
c: R_ARM_THM_ALU_ABS_G1_NC foo
e: 021b lsls r3, r3, #8
10: 3300 adds r3, #0
10: R_ARM_THM_ALU_ABS_G0_NC foo
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* elf32-arm.c (THM2_MAX_FWD_BRANCH_OFFSET): Define.
(THM2_MAX_BWD_BRANCH_OFFSET): Define.
(ARM_MAX_FWD_BRANCH_OFFSET): Define.
(ARM_MAX_BWD_BRANCH_OFFSET): Define.
(THM_MAX_FWD_BRANCH_OFFSET): Define.
(THM_MAX_BWD_BRANCH_OFFSET): Define.
(arm_long_branch_stub): Define.
(arm_pic_long_branch_stub): Define.
(arm_thumb_v4t_long_branch_stub): Define.
(arm_thumb_thumb_long_branch_stub): Define.
(arm_thumb_arm_v4t_long_branch_stub): Define.
(STUB_SUFFIX): Define.
(elf32_arm_stub_type): Define.
(elf32_arm_stub_hash_entry): Define.
(elf32_arm_link_hash_entry): Add stub_cache field.
(arm_stub_hash_lookup): Define.
(elf32_arm_link_hash_table): Add stub_hash_table, stub_bfd,
add_stub_section, layout_sections_again, stub_group, bfd_count,
top_index, input_list fields.
(elf32_arm_link_hash_newfunc): Init new field.
(stub_hash_newfunc): New function.
(elf32_arm_link_hash_table_create): Init stub_hash_table.
(elf32_arm_hash_table_free): New function.
(arm_type_of_stub): New function.
(elf32_arm_stub_name): New function.
(elf32_arm_get_stub_entry): New function.
(elf32_arm_stub_add_mapping_symbol): New function.
(elf32_arm_add_stub): New function.
(arm_build_one_stub): New function.
(arm_size_one_stub): New function.
(elf32_arm_setup_section_lists): New function.
(elf32_arm_next_input_section): New function.
(group_sections): New function.
(elf32_arm_size_stubs): New function.
(elf32_arm_build_stubs): New function.
(bfd_elf32_arm_add_glue_sections_to_bfd): Skip stub sections.
(bfd_elf32_arm_process_before_allocation): No longer handle
R_ARM_CALL and R_ARM_THM_CALL.
(using_thumb_only): New function.
(elf32_arm_final_link_relocate): Redirect calls to stub if range
exceeds encoding capabilities.
(bfd_elf32_bfd_link_hash_table_free): Define.
* bfd-in.h (R_ARM_max): Fix value to 130.
(elf32_arm_setup_section_lists): Protype.
(elf32_arm_next_input_section): Protype.
(elf32_arm_size_stubs): Protype.
(elf32_arm_build_stubs): Protype.
ld/
* emultempl/armelf.em (build_section_lists): New function.
(stub_file): Define.
(need_laying_out): Define.
(group_size): Define.
(hook_stub_info): Define.
(hook_in_stub): New function.
(elf32_arm_add_stub_section): New function.
(gldarm_layout_sections_again): New function.
(gld${EMULATION_NAME}_finish): Replace arm_elf_finish(). Generate
stubs for long calls if needed.
(arm_elf_create_output_section_statements): create stub_file bfd.
(arm_for_each_input_file_wrapper): New function.
(arm_lang_for_each_input_file): New function.
(lang_for_each_input_file): Define.
(PARSE_AND_LIST_PROLOGUE): Add option token OPTION_STUBGROUP_SIZE.
(PARSE_AND_LIST_LONGOPTS): Add option stub-group-size.
(PARSE_AND_LIST_OPTIONS): Add option stub-group-size.
(PARSE_AND_LIST_ARGS_CASES): Add OPTION_STUBGROUP_SIZE case.
(LDEMUL_FINISH): Update to gld${EMULATION_NAME}_finish.
* ld/lang.c (print_input_statement): Skip if bfd has
BFD_LINKER_CREATED.
ld/testsuite
* ld-arm/arm-elf.exp (armelftests): Add farcall-arm-arm,
farcall-arm-arm-pic-veneer, farcall-arm-arm-be8 farcall-arm-thumb,
farcall-arm-thumb-blx, farcall-arm-thumb-pic-veneer,
farcall-arm-thumb-blx-pic-veneer, farcall-thumb-thumb,
farcall-thumb-thumb-pic-veneer, farcall-thumb-thumb-blx,
farcall-thumb-thumb-m, farcall-thumb-thumb-m-pic-veneer,
farcall-thumb-thumb-blx-pic-veneer, farcall-thumb-arm,
farcall-thumb-arm-pic-veneer, farcall-thumb-arm-blx,
farcall-thumb-arm-blx-pic-veneer.
Change thumb2-bl-as-thumb1-bad, thumb2-bl-bad.
* ld-arm/thumb2-bl-as-thumb1-bad.d: Reflects farcall stub
generation.
* ld-arm/thumb2-bl-bad.d: Likewise.
* ld-arm/thumb2-bl-as-thumb1-bad.s: Update comments.
* ld-arm/thumb2-bl-bad.s: Likewise.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* bfd-in2.h, libbfd.h: Regenerated.
* reloc.c: Add ARM TLS relocations.
* elf32-arm.c (elf32_arm_howto_table): Add dynamic TLS
relocations.
(elf32_arm_tls_gd32_howto, elf32_arm_tls_ldo32_howto)
(elf32_arm_tls_ldm32_howto, elf32_arm_tls_le32_howto)
(elf32_arm_tls_ie32_howto): New.
(elf32_arm_howto_from_type): Support TLS relocations.
(elf32_arm_reloc_map): Likewise.
(elf32_arm_reloc_type_lookup): Likewise.
(TCB_SIZE): Define.
(struct elf32_arm_obj_tdata): New.
(elf32_arm_tdata, elf32_arm_local_got_tls_type): Define.
(elf32_arm_mkobject): New function.
(struct elf32_arm_relocs_copied): Add pc_count.
(elf32_arm_hash_entry, GOT_UNKNOWN, GOT_NORMAL, GOT_TLS_GD)
(GOT_TLS_IE): Define.
(struct elf32_arm_link_hash_table): Add tls_ldm_got.
(elf32_arm_link_hash_newfunc): Initialize tls_type.
(elf32_arm_copy_indirect_symbol): Copy pc_count and tls_type.
(elf32_arm_link_hash_table_create): Initialize tls_ldm_got.
(dtpoff_base, tpoff): New functions.
(elf32_arm_final_link_relocate): Handle TLS relocations.
(IS_ARM_TLS_RELOC): Define.
(elf32_arm_relocate_section): Warn about TLS mismatches.
(elf32_arm_gc_sweep_hook): Handle TLS relocations and pc_count.
(elf32_arm_check_relocs): Detect invalid symbol indexes. Handle
TLS relocations and pc_count.
(elf32_arm_adjust_dynamic_symbol): Check non_got_ref.
(allocate_dynrelocs): Handle TLS. Bind REL32 relocs to local
calls.
(elf32_arm_size_dynamic_sections): Handle TLS.
(elf32_arm_finish_dynamic_symbol): Likewise.
(bfd_elf32_mkobject): Define.
gas/
* config/tc-arm.c (arm_parse_reloc): Add TLS relocations.
(md_apply_fix3): Mark TLS symbols.
(tc_gen_reloc): Handle TLS relocations.
(arm_fix_adjustable): Ignore TLS relocations.
(s_arm_elf_cons): Support expressions after decorated symbols.
gas/testuite/
* gas/arm/tls.s, gas/arm/tls.d: New files.
* gas/arm/arm.exp: Run TLS test.
include/elf/
* arm.h: Add TLS relocations.
ld/testsuite/
* ld-arm/tls-lib.s, ld-arm/tls-lib.d, ld-arm/tls-lib.r,
ld-arm/tls-app.s, ld-arm/tls-app.d, ld-arm/tls-app.r: New files.
* ld-arm/arm-lib.ld, ld-arm/arm-dyn.ld: Increase data segment
alignment.
* ld-arm/arm-elf.exp: Run TLS tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* bfd-in2.h, libbfd.h: Regenerated.
* reloc.c: Add ARM TLS relocations.
* elf32-arm.c (elf32_arm_howto_table): Add dynamic TLS
relocations.
(elf32_arm_tls_gd32_howto, elf32_arm_tls_ldo32_howto)
(elf32_arm_tls_ldm32_howto, elf32_arm_tls_le32_howto)
(elf32_arm_tls_ie32_howto): New.
(elf32_arm_howto_from_type): Support TLS relocations.
(elf32_arm_reloc_map): Likewise.
(elf32_arm_reloc_type_lookup): Likewise.
(TCB_SIZE): Define.
(struct elf32_arm_obj_tdata): New.
(elf32_arm_tdata, elf32_arm_local_got_tls_type): Define.
(elf32_arm_mkobject): New function.
(struct elf32_arm_relocs_copied): Add pc_count.
(elf32_arm_hash_entry, GOT_UNKNOWN, GOT_NORMAL, GOT_TLS_GD)
(GOT_TLS_IE): Define.
(struct elf32_arm_link_hash_table): Add tls_ldm_got.
(elf32_arm_link_hash_newfunc): Initialize tls_type.
(elf32_arm_copy_indirect_symbol): Copy pc_count and tls_type.
(elf32_arm_link_hash_table_create): Initialize tls_ldm_got.
(dtpoff_base, tpoff): New functions.
(elf32_arm_final_link_relocate): Handle TLS relocations.
(IS_ARM_TLS_RELOC): Define.
(elf32_arm_relocate_section): Warn about TLS mismatches.
(elf32_arm_gc_sweep_hook): Handle TLS relocations and pc_count.
(elf32_arm_check_relocs): Detect invalid symbol indexes. Handle
TLS relocations and pc_count.
(elf32_arm_adjust_dynamic_symbol): Check non_got_ref.
(allocate_dynrelocs): Handle TLS. Bind REL32 relocs to local
calls.
(elf32_arm_size_dynamic_sections): Handle TLS.
(elf32_arm_finish_dynamic_symbol): Likewise.
(bfd_elf32_mkobject): Define.
gas/
* config/tc-arm.c (arm_parse_reloc): Add TLS relocations.
(md_apply_fix3): Mark TLS symbols.
(tc_gen_reloc): Handle TLS relocations.
(arm_fix_adjustable): Ignore TLS relocations.
(s_arm_elf_cons): Support expressions after decorated symbols.
gas/testuite/
* gas/arm/tls.s, gas/arm/tls.d: New files.
* gas/arm/arm.exp: Run TLS test.
include/elf/
* arm.h: Add TLS relocations.
ld/testsuite/
* ld-arm/tls-lib.s, ld-arm/tls-lib.d, ld-arm/tls-lib.r,
ld-arm/tls-app.s, ld-arm/tls-app.d, ld-arm/tls-app.r: New files.
* ld-arm/arm-lib.ld, ld-arm/arm-dyn.ld: Increase data segment
alignment.
* ld-arm/arm-elf.exp: Run TLS tests.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* reloc.c (BFD_RELOC_ARM_TLS_GOTDESC, BFD_RELOC_ARM_TLS_CALL,
BFD_RELOC_ARM_THM_TLS_CALL, BFD_RELOC_ARM_TLS_DESCSEQ,
BFD_RELOC_ARM_THM_TLS_DESCSEQ, BFD_RELOC_ARM_TLS_DESC): New
relocations.
* libbfd.h: Rebuilt.
* bfd-in2.h: Rebuilt.
* elf32-arm.c (elf32_arm_howto_table_1): Add new relocations.
(elf32_arm_reloc_map): Likewise.
(tls_trampoline, dl_tlsdesc_lazy_trampoline): New PLT templates.
(elf32_arm_stub_long_branch_any_tls_pic,
elf32_arm_stub_long_branch_v4t_thumb_tls_pic): New stub templates.
(DEF_STUBS): Add new stubs.
(struct_elf_arm_obj_data): Add local_tlsdesc_gotent field.
(elf32_arm_local_tlsdesc_gotent): New.
(GOT_TLS_GDESC): New mask.
(GOT_TLS_GD_ANY): Define.
(struct elf32_arm_link_hash_entry): Add tlsdesc_got field.
(elf32_arm_compute_jump_table_size): New.
(struct elf32_arm_link_hash_table): Add next_tls_desc_index,
num_tls_desc, dt_tlsdesc_plt, dt_tlsdesc_got, tls_trampoline,
sgotplt_jump_table_size fields.
(elf32_arm_link_hash_newfunc): Initialize tlsdesc_got field.
(elf32_arm_link_hash_table_create): Initialize new fields.
(arm_type_of_stub): Check TLS desc relocs too.
(elf32_arm_stub_name): TLS desc relocs can be shared.
(elf32_arm_tls_transition): Determine relaxation.
(arm_stub_required_alignment): Add tls stubs.
(elf32_arm_size_stubs): Likewise.
(elf32_arm_tls_relax): Perform TLS relaxing.
(elf32_arm_final_link_relocate): Process TLS DESC relocations.
(IS_ARM_TLS_GNU_RELOC): New.
(IS_ARM_TLS_RELOC): Use it.
(elf32_arm_relocate_section): Perform TLS relaxing.
(elf32_arm_check_relocs): Anticipate TLS relaxing, process tls
desc relocations.
(allocate_dynrelocs): Allocate tls desc relcoations.
(elf32_arm_output_arch_local_syms): Emit tls trampoline mapping
symbols.
(elf32_arm_size_dynamic_sections): Allocate tls trampolines and
got slots.
(elf32_arm_always_size_sections): New. Create _TLS_MODULE_BASE
symbol.
(elf32_arm_finish_dynamic_symbol): Adjust.
(arm_put_trampoline): New.
(elf32_arm_finish_dynamic_sections): Emit new dynamic tags and tls
trampolines.
(elf_backend_always_size_sections): Define.
include/elf/
* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
relocations.
gas/
* doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
.tlsdescseq directive.
* config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
following a symbol.
(s_arm_tls_descseq): New directive.
(md_pseudo_table): Add it.
(encode_branch): Allow TLS_CALL relocs too.
(do_t_blx, do_t_branch23): Use encode_branch.
(reloc_names): Add tlsdesc and tlscall.
(md_apply_fix): Process tls desc relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/tls.s: Add tlsdesc tests.
* gas/arm/tls.d: Adjust.
ld/testsuite/
* ld-arm/arm-elf.exp: Added tests for new TLS handling
relocations.
* ld-arm/tls-descrelax-be32.d: New.
* ld-arm/tls-descrelax-be32.s: New.
* ld-arm/tls-descrelax-be8.d: New.
* ld-arm/tls-descrelax-be8.s: New.
* ld-arm/tls-descrelax-v7.d: New.
* ld-arm/tls-descrelax-v7.s: New.
* ld-arm/tls-descrelax.d: New.
* ld-arm/tls-descrelax.s: New.
* ld-arm/tls-descseq.d: New.
* ld-arm/tls-descseq.r: New.
* ld-arm/tls-descseq.s: New.
* ld-arm/tls-gdesc-got.d: New.
* ld-arm/tls-gdesc-got.s: New.
* ld-arm/tls-gdesc-nlazy.g: New.
* ld-arm/tls-gdesc-nlazy.s: New.
* ld-arm/tls-gdesc.d: New.
* ld-arm/tls-gdesc.r: New.
* ld-arm/tls-gdesc.s: New.
* ld-arm/tls-gdierelax.d: New.
* ld-arm/tls-gdierelax.s: New.
* ld-arm/tls-gdierelax2.d: New.
* ld-arm/tls-gdierelax2.s: New.
* ld-arm/tls-gdlerelax.d: New.
* ld-arm/tls-gdlerelax.s: New.
* ld-arm/tls-lib-loc.d: New.
* ld-arm/tls-lib-loc.r: New.
* ld-arm/tls-lib-loc.s: New.
* ld-arm/tls-longplt-lib.d: New.
* ld-arm/tls-longplt-lib.s: New.
* ld-arm/tls-longplt.d: New.
* ld-arm/tls-longplt.s: New.
* ld-arm/tls-mixed.r: New.
* ld-arm/tls-mixed.s: New.
* ld-arm/tls-thumb1.d: New.
* ld-arm/tls-thumb1.s: New.
* ld-arm/arm-elf.exp: New.
readelf ngettext fixes
This patch is a first pass at fixing readelf message pluralization.
I've deliberately not fixed the "out of memory" errors since it's very
unlikely that they will ever be complaining about not being able to
allocate for a single entry, and a few others where the size is very
unlikely to be 1 byte.
Then there are messages like this one:
"Out of %lu items there are %zu bucket clashes (longest of %zu entries).\n"
I suppose this could be split into three parts, "Of %lu items ",
"there are %zu bucket clashes ", and "(longest of %zu entries).\n",
each part being printed separately, but that might not be ideal for
sentence construction in other languages. For now I'm punting on this
one.
Changes to readelf output require lots of testsuite adjustment..
binutils/
* dwarf.c (read_uleb128): Properly pluralize messages.
(display_debug_lines_raw, display_debug_loc): Likewise.
(display_debug_names, process_cu_tu_index): Likewise.
* od-macho.c (dump_code_signature_superblob): Likewise.
* readelf.c (process_program_headers): Likewise.
(process_section_header, process_relocs): Likewise.
(hppa_process_unwind, arm_process_unwind): Likewise.
(process_dynamic_section, process_version_sections): Likewise.
(process_symbol_table, process_syminfo): Likewise.
(apply_relocations, process_mips_specific): Likewise.
(process_gnu_liblist, process_notes_at): Likewise.
(process_archive): Likewise.
* testsuite/binutils-all/dw2-1.W,
* testsuite/binutils-all/dw2-3.W,
* testsuite/binutils-all/dw2-3gabi.W,
* testsuite/binutils-all/dw5.S,
* testsuite/binutils-all/dw5.W,
* testsuite/binutils-all/i386/compressed-1a.d,
* testsuite/binutils-all/libdw2-compressedgabi.out,
* testsuite/binutils-all/objdump.W,
* testsuite/binutils-all/readelf.r,
* testsuite/binutils-all/readelf.r-64,
* testsuite/binutils-all/x86-64/compressed-1a.d: Update
for pluralization fixes.
gas/
* testsuite/gas/arm/got_prel.d,
* testsuite/gas/elf/dwarf2-1.d,
* testsuite/gas/elf/dwarf2-2.d,
* testsuite/gas/elf/dwarf2-3.d,
* testsuite/gas/elf/dwarf2-5.d,
* testsuite/gas/elf/dwarf2-6.d,
* testsuite/gas/i386/debug1.d,
* testsuite/gas/i386/dw2-compress-1.d,
* testsuite/gas/i386/dw2-compress-3a.d,
* testsuite/gas/i386/dw2-compress-3b.d,
* testsuite/gas/i386/dw2-compressed-1.d,
* testsuite/gas/i386/dw2-compressed-3a.d,
* testsuite/gas/i386/dw2-compressed-3b.d,
* testsuite/gas/i386/ilp32/x86-64-localpic.d,
* testsuite/gas/i386/localpic.d,
* testsuite/gas/i386/x86-64-localpic.d,
* testsuite/gas/ia64/pr13167.d,
* testsuite/gas/mips/loc-swap-2.d,
* testsuite/gas/mips/loc-swap.d,
* testsuite/gas/mips/micromips@loc-swap-2.d,
* testsuite/gas/mips/micromips@loc-swap.d,
* testsuite/gas/mips/mips16-dwarf2-n32.d,
* testsuite/gas/mips/mips16-dwarf2.d,
* testsuite/gas/mips/mips16@loc-swap-2.d,
* testsuite/gas/mips/mips16@loc-swap.d,
* testsuite/gas/mips/mips16e@loc-swap.d,
* testsuite/gas/mmix/bspec-1.d,
* testsuite/gas/mmix/bspec-2.d,
* testsuite/gas/tic6x/unwind-1.d,
* testsuite/gas/tic6x/unwind-2.d,
* testsuite/gas/tic6x/unwind-3.d: Update for pluralization
fixes.
ld/
* testsuite/ld-aarch64/ifunc-13.d,
* testsuite/ld-aarch64/ifunc-15.d,
* testsuite/ld-aarch64/ifunc-20.d,
* testsuite/ld-alpha/tlsbin.rd,
* testsuite/ld-alpha/tlspic.rd,
* testsuite/ld-arm/ifunc-3.rd,
* testsuite/ld-arm/ifunc-9.rd,
* testsuite/ld-arm/unwind-mix.d,
* testsuite/ld-arm/unwind-rel.d,
* testsuite/ld-cris/hiddef1.d,
* testsuite/ld-cris/libdso-13.d,
* testsuite/ld-cris/libdso-2.d,
* testsuite/ld-cris/pr16044.d,
* testsuite/ld-cris/tls-local-63.d,
* testsuite/ld-cris/tls-local-64.d,
* testsuite/ld-cris/tls-und-38.d,
* testsuite/ld-cris/tls-und-42.d,
* testsuite/ld-cris/tls-und-46.d,
* testsuite/ld-cris/tls-und-50.d,
* testsuite/ld-cris/weakref3.d,
* testsuite/ld-cris/weakref4.d,
* testsuite/ld-elf/comm-data2r.rd,
* testsuite/ld-elf/discard1.d,
* testsuite/ld-elf/discard2.d,
* testsuite/ld-elf/pr19539.d,
* testsuite/ld-elf/pr22374-1.r,
* testsuite/ld-elf/pr22374-2.r,
* testsuite/ld-i386/combreloc.d,
* testsuite/ld-i386/emit-relocs-nacl.rd,
* testsuite/ld-i386/emit-relocs.rd,
* testsuite/ld-i386/pr13302.d,
* testsuite/ld-i386/pr17709-nacl.rd,
* testsuite/ld-i386/pr17709.rd,
* testsuite/ld-i386/pr19539.d,
* testsuite/ld-i386/pr19615.d,
* testsuite/ld-i386/pr19636-1a.d,
* testsuite/ld-i386/pr19636-1e.d,
* testsuite/ld-i386/pr19636-1f.d,
* testsuite/ld-i386/pr19636-2a.d,
* testsuite/ld-i386/pr19636-2b.d,
* testsuite/ld-i386/pr19636-2d-nacl.d,
* testsuite/ld-i386/pr19636-2e-nacl.d,
* testsuite/ld-i386/pr19636-3a.d,
* testsuite/ld-i386/pr19636-3d.d,
* testsuite/ld-i386/pr19636-3e.d,
* testsuite/ld-i386/pr19636-4a.d,
* testsuite/ld-i386/pr19645.d,
* testsuite/ld-i386/pr19827-nacl.rd,
* testsuite/ld-i386/pr19827.rd,
* testsuite/ld-i386/pr20253-4a.d,
* testsuite/ld-i386/pr20253-4b.d,
* testsuite/ld-i386/pr20253-5.d,
* testsuite/ld-i386/tlsbin-nacl.rd,
* testsuite/ld-i386/tlsbin.rd,
* testsuite/ld-i386/tlspic-nacl.rd,
* testsuite/ld-i386/tlspic.rd,
* testsuite/ld-i386/undefweakb.d,
* testsuite/ld-ia64/tlsbin.rd,
* testsuite/ld-ia64/tlspic.rd,
* testsuite/ld-ifunc/ifunc-13-i386.d,
* testsuite/ld-ifunc/ifunc-13-x86-64.d,
* testsuite/ld-ifunc/ifunc-15-i386.d,
* testsuite/ld-ifunc/ifunc-15-x86-64.d,
* testsuite/ld-ifunc/ifunc-20-i386.d,
* testsuite/ld-ifunc/ifunc-20-x86-64.d,
* testsuite/ld-ifunc/ifunc-23a-x86.d,
* testsuite/ld-ifunc/ifunc-23b-x86.d,
* testsuite/ld-ifunc/ifunc-23c-x86.d,
* testsuite/ld-ifunc/ifunc-24a-x86.d,
* testsuite/ld-ifunc/ifunc-24b-x86.d,
* testsuite/ld-ifunc/ifunc-24c-x86.d,
* testsuite/ld-ifunc/ifunc-25a-x86.d,
* testsuite/ld-ifunc/ifunc-25b-x86.d,
* testsuite/ld-ifunc/ifunc-25c-x86.d,
* testsuite/ld-m68k/got-1.d,
* testsuite/ld-mips-elf/vxworks1.rd,
* testsuite/ld-powerpc/ambiguousv1.d,
* testsuite/ld-powerpc/ambiguousv1b.d,
* testsuite/ld-powerpc/ambiguousv2.d,
* testsuite/ld-powerpc/ambiguousv2b.d,
* testsuite/ld-powerpc/tlsexe.r,
* testsuite/ld-powerpc/tlsexe32.r,
* testsuite/ld-powerpc/tlsexetoc.r,
* testsuite/ld-powerpc/tlsso.r,
* testsuite/ld-powerpc/tlsso32.r,
* testsuite/ld-powerpc/tlstocso.r,
* testsuite/ld-powerpc/vle-multiseg-1.d,
* testsuite/ld-powerpc/vle-multiseg-2.d,
* testsuite/ld-powerpc/vle-multiseg-3.d,
* testsuite/ld-s390/tlsbin.rd,
* testsuite/ld-s390/tlsbin_64.rd,
* testsuite/ld-s390/tlspic.rd,
* testsuite/ld-s390/tlspic_64.rd,
* testsuite/ld-sh/ld-r-1.d,
* testsuite/ld-sh/sh64/gotplt.d,
* testsuite/ld-sh/shared-1.d,
* testsuite/ld-sh/tlsbin-2.d,
* testsuite/ld-sh/tlspic-2.d,
* testsuite/ld-sparc/gotop32.rd,
* testsuite/ld-sparc/gotop64.rd,
* testsuite/ld-sparc/tlssunpic32.rd,
* testsuite/ld-sparc/tlssunpic64.rd,
* testsuite/ld-sparc/vxworks1-lib.rd,
* testsuite/ld-tic6x/shlib-app-1.rd,
* testsuite/ld-tic6x/shlib-app-1b.rd,
* testsuite/ld-tic6x/shlib-app-1r.rd,
* testsuite/ld-tic6x/shlib-app-1rb.rd,
* testsuite/ld-tic6x/shlib-noindex.rd,
* testsuite/ld-vax-elf/export-class-data.rd,
* testsuite/ld-x86-64/pr13082-1a.d,
* testsuite/ld-x86-64/pr13082-1b.d,
* testsuite/ld-x86-64/pr13082-2a.d,
* testsuite/ld-x86-64/pr13082-2b.d,
* testsuite/ld-x86-64/pr13082-3a.d,
* testsuite/ld-x86-64/pr13082-3c.d,
* testsuite/ld-x86-64/pr13082-4a.d,
* testsuite/ld-x86-64/pr13082-5a.d,
* testsuite/ld-x86-64/pr13082-5b.d,
* testsuite/ld-x86-64/pr13082-6a.d,
* testsuite/ld-x86-64/pr13082-6b.d,
* testsuite/ld-x86-64/pr17709-nacl.rd,
* testsuite/ld-x86-64/pr17709.rd,
* testsuite/ld-x86-64/pr19539a.d,
* testsuite/ld-x86-64/pr19539b.d,
* testsuite/ld-x86-64/pr19615.d,
* testsuite/ld-x86-64/pr19636-1a.d,
* testsuite/ld-x86-64/pr19636-1d.d,
* testsuite/ld-x86-64/pr19636-1e.d,
* testsuite/ld-x86-64/pr19636-2a.d,
* testsuite/ld-x86-64/pr19636-2e.d,
* testsuite/ld-x86-64/pr19636-2f.d,
* testsuite/ld-x86-64/pr19636-3a.d,
* testsuite/ld-x86-64/pr19645.d,
* testsuite/ld-x86-64/pr19807-2b.d,
* testsuite/ld-x86-64/pr19807-2d.d,
* testsuite/ld-x86-64/pr19827-nacl.rd,
* testsuite/ld-x86-64/pr19827.rd,
* testsuite/ld-x86-64/pr20253-4a.d,
* testsuite/ld-x86-64/pr20253-4b.d,
* testsuite/ld-x86-64/pr20253-4d.d,
* testsuite/ld-x86-64/pr20253-4e.d,
* testsuite/ld-x86-64/pr20253-5a.d,
* testsuite/ld-x86-64/pr20253-5b.d,
* testsuite/ld-x86-64/tlsbin-nacl.rd,
* testsuite/ld-x86-64/tlsbin.rd,
* testsuite/ld-x86-64/tlspic-nacl.rd,
* testsuite/ld-x86-64/tlspic.rd,
* testsuite/ld-x86-64/tlspic2-nacl.rd: Update for
pluralization fixes.
readelf ngettext fixes
This patch is a first pass at fixing readelf message pluralization.
I've deliberately not fixed the "out of memory" errors since it's very
unlikely that they will ever be complaining about not being able to
allocate for a single entry, and a few others where the size is very
unlikely to be 1 byte.
Then there are messages like this one:
"Out of %lu items there are %zu bucket clashes (longest of %zu entries).\n"
I suppose this could be split into three parts, "Of %lu items ",
"there are %zu bucket clashes ", and "(longest of %zu entries).\n",
each part being printed separately, but that might not be ideal for
sentence construction in other languages. For now I'm punting on this
one.
Changes to readelf output require lots of testsuite adjustment..
binutils/
* dwarf.c (read_uleb128): Properly pluralize messages.
(display_debug_lines_raw, display_debug_loc): Likewise.
(display_debug_names, process_cu_tu_index): Likewise.
* od-macho.c (dump_code_signature_superblob): Likewise.
* readelf.c (process_program_headers): Likewise.
(process_section_header, process_relocs): Likewise.
(hppa_process_unwind, arm_process_unwind): Likewise.
(process_dynamic_section, process_version_sections): Likewise.
(process_symbol_table, process_syminfo): Likewise.
(apply_relocations, process_mips_specific): Likewise.
(process_gnu_liblist, process_notes_at): Likewise.
(process_archive): Likewise.
* testsuite/binutils-all/dw2-1.W,
* testsuite/binutils-all/dw2-3.W,
* testsuite/binutils-all/dw2-3gabi.W,
* testsuite/binutils-all/dw5.S,
* testsuite/binutils-all/dw5.W,
* testsuite/binutils-all/i386/compressed-1a.d,
* testsuite/binutils-all/libdw2-compressedgabi.out,
* testsuite/binutils-all/objdump.W,
* testsuite/binutils-all/readelf.r,
* testsuite/binutils-all/readelf.r-64,
* testsuite/binutils-all/x86-64/compressed-1a.d: Update
for pluralization fixes.
gas/
* testsuite/gas/arm/got_prel.d,
* testsuite/gas/elf/dwarf2-1.d,
* testsuite/gas/elf/dwarf2-2.d,
* testsuite/gas/elf/dwarf2-3.d,
* testsuite/gas/elf/dwarf2-5.d,
* testsuite/gas/elf/dwarf2-6.d,
* testsuite/gas/i386/debug1.d,
* testsuite/gas/i386/dw2-compress-1.d,
* testsuite/gas/i386/dw2-compress-3a.d,
* testsuite/gas/i386/dw2-compress-3b.d,
* testsuite/gas/i386/dw2-compressed-1.d,
* testsuite/gas/i386/dw2-compressed-3a.d,
* testsuite/gas/i386/dw2-compressed-3b.d,
* testsuite/gas/i386/ilp32/x86-64-localpic.d,
* testsuite/gas/i386/localpic.d,
* testsuite/gas/i386/x86-64-localpic.d,
* testsuite/gas/ia64/pr13167.d,
* testsuite/gas/mips/loc-swap-2.d,
* testsuite/gas/mips/loc-swap.d,
* testsuite/gas/mips/micromips@loc-swap-2.d,
* testsuite/gas/mips/micromips@loc-swap.d,
* testsuite/gas/mips/mips16-dwarf2-n32.d,
* testsuite/gas/mips/mips16-dwarf2.d,
* testsuite/gas/mips/mips16@loc-swap-2.d,
* testsuite/gas/mips/mips16@loc-swap.d,
* testsuite/gas/mips/mips16e@loc-swap.d,
* testsuite/gas/mmix/bspec-1.d,
* testsuite/gas/mmix/bspec-2.d,
* testsuite/gas/tic6x/unwind-1.d,
* testsuite/gas/tic6x/unwind-2.d,
* testsuite/gas/tic6x/unwind-3.d: Update for pluralization
fixes.
ld/
* testsuite/ld-aarch64/ifunc-13.d,
* testsuite/ld-aarch64/ifunc-15.d,
* testsuite/ld-aarch64/ifunc-20.d,
* testsuite/ld-alpha/tlsbin.rd,
* testsuite/ld-alpha/tlspic.rd,
* testsuite/ld-arm/ifunc-3.rd,
* testsuite/ld-arm/ifunc-9.rd,
* testsuite/ld-arm/unwind-mix.d,
* testsuite/ld-arm/unwind-rel.d,
* testsuite/ld-cris/hiddef1.d,
* testsuite/ld-cris/libdso-13.d,
* testsuite/ld-cris/libdso-2.d,
* testsuite/ld-cris/pr16044.d,
* testsuite/ld-cris/tls-local-63.d,
* testsuite/ld-cris/tls-local-64.d,
* testsuite/ld-cris/tls-und-38.d,
* testsuite/ld-cris/tls-und-42.d,
* testsuite/ld-cris/tls-und-46.d,
* testsuite/ld-cris/tls-und-50.d,
* testsuite/ld-cris/weakref3.d,
* testsuite/ld-cris/weakref4.d,
* testsuite/ld-elf/comm-data2r.rd,
* testsuite/ld-elf/discard1.d,
* testsuite/ld-elf/discard2.d,
* testsuite/ld-elf/pr19539.d,
* testsuite/ld-elf/pr22374-1.r,
* testsuite/ld-elf/pr22374-2.r,
* testsuite/ld-i386/combreloc.d,
* testsuite/ld-i386/emit-relocs-nacl.rd,
* testsuite/ld-i386/emit-relocs.rd,
* testsuite/ld-i386/pr13302.d,
* testsuite/ld-i386/pr17709-nacl.rd,
* testsuite/ld-i386/pr17709.rd,
* testsuite/ld-i386/pr19539.d,
* testsuite/ld-i386/pr19615.d,
* testsuite/ld-i386/pr19636-1a.d,
* testsuite/ld-i386/pr19636-1e.d,
* testsuite/ld-i386/pr19636-1f.d,
* testsuite/ld-i386/pr19636-2a.d,
* testsuite/ld-i386/pr19636-2b.d,
* testsuite/ld-i386/pr19636-2d-nacl.d,
* testsuite/ld-i386/pr19636-2e-nacl.d,
* testsuite/ld-i386/pr19636-3a.d,
* testsuite/ld-i386/pr19636-3d.d,
* testsuite/ld-i386/pr19636-3e.d,
* testsuite/ld-i386/pr19636-4a.d,
* testsuite/ld-i386/pr19645.d,
* testsuite/ld-i386/pr19827-nacl.rd,
* testsuite/ld-i386/pr19827.rd,
* testsuite/ld-i386/pr20253-4a.d,
* testsuite/ld-i386/pr20253-4b.d,
* testsuite/ld-i386/pr20253-5.d,
* testsuite/ld-i386/tlsbin-nacl.rd,
* testsuite/ld-i386/tlsbin.rd,
* testsuite/ld-i386/tlspic-nacl.rd,
* testsuite/ld-i386/tlspic.rd,
* testsuite/ld-i386/undefweakb.d,
* testsuite/ld-ia64/tlsbin.rd,
* testsuite/ld-ia64/tlspic.rd,
* testsuite/ld-ifunc/ifunc-13-i386.d,
* testsuite/ld-ifunc/ifunc-13-x86-64.d,
* testsuite/ld-ifunc/ifunc-15-i386.d,
* testsuite/ld-ifunc/ifunc-15-x86-64.d,
* testsuite/ld-ifunc/ifunc-20-i386.d,
* testsuite/ld-ifunc/ifunc-20-x86-64.d,
* testsuite/ld-ifunc/ifunc-23a-x86.d,
* testsuite/ld-ifunc/ifunc-23b-x86.d,
* testsuite/ld-ifunc/ifunc-23c-x86.d,
* testsuite/ld-ifunc/ifunc-24a-x86.d,
* testsuite/ld-ifunc/ifunc-24b-x86.d,
* testsuite/ld-ifunc/ifunc-24c-x86.d,
* testsuite/ld-ifunc/ifunc-25a-x86.d,
* testsuite/ld-ifunc/ifunc-25b-x86.d,
* testsuite/ld-ifunc/ifunc-25c-x86.d,
* testsuite/ld-m68k/got-1.d,
* testsuite/ld-mips-elf/vxworks1.rd,
* testsuite/ld-powerpc/ambiguousv1.d,
* testsuite/ld-powerpc/ambiguousv1b.d,
* testsuite/ld-powerpc/ambiguousv2.d,
* testsuite/ld-powerpc/ambiguousv2b.d,
* testsuite/ld-powerpc/tlsexe.r,
* testsuite/ld-powerpc/tlsexe32.r,
* testsuite/ld-powerpc/tlsexetoc.r,
* testsuite/ld-powerpc/tlsso.r,
* testsuite/ld-powerpc/tlsso32.r,
* testsuite/ld-powerpc/tlstocso.r,
* testsuite/ld-powerpc/vle-multiseg-1.d,
* testsuite/ld-powerpc/vle-multiseg-2.d,
* testsuite/ld-powerpc/vle-multiseg-3.d,
* testsuite/ld-s390/tlsbin.rd,
* testsuite/ld-s390/tlsbin_64.rd,
* testsuite/ld-s390/tlspic.rd,
* testsuite/ld-s390/tlspic_64.rd,
* testsuite/ld-sh/ld-r-1.d,
* testsuite/ld-sh/sh64/gotplt.d,
* testsuite/ld-sh/shared-1.d,
* testsuite/ld-sh/tlsbin-2.d,
* testsuite/ld-sh/tlspic-2.d,
* testsuite/ld-sparc/gotop32.rd,
* testsuite/ld-sparc/gotop64.rd,
* testsuite/ld-sparc/tlssunpic32.rd,
* testsuite/ld-sparc/tlssunpic64.rd,
* testsuite/ld-sparc/vxworks1-lib.rd,
* testsuite/ld-tic6x/shlib-app-1.rd,
* testsuite/ld-tic6x/shlib-app-1b.rd,
* testsuite/ld-tic6x/shlib-app-1r.rd,
* testsuite/ld-tic6x/shlib-app-1rb.rd,
* testsuite/ld-tic6x/shlib-noindex.rd,
* testsuite/ld-vax-elf/export-class-data.rd,
* testsuite/ld-x86-64/pr13082-1a.d,
* testsuite/ld-x86-64/pr13082-1b.d,
* testsuite/ld-x86-64/pr13082-2a.d,
* testsuite/ld-x86-64/pr13082-2b.d,
* testsuite/ld-x86-64/pr13082-3a.d,
* testsuite/ld-x86-64/pr13082-3c.d,
* testsuite/ld-x86-64/pr13082-4a.d,
* testsuite/ld-x86-64/pr13082-5a.d,
* testsuite/ld-x86-64/pr13082-5b.d,
* testsuite/ld-x86-64/pr13082-6a.d,
* testsuite/ld-x86-64/pr13082-6b.d,
* testsuite/ld-x86-64/pr17709-nacl.rd,
* testsuite/ld-x86-64/pr17709.rd,
* testsuite/ld-x86-64/pr19539a.d,
* testsuite/ld-x86-64/pr19539b.d,
* testsuite/ld-x86-64/pr19615.d,
* testsuite/ld-x86-64/pr19636-1a.d,
* testsuite/ld-x86-64/pr19636-1d.d,
* testsuite/ld-x86-64/pr19636-1e.d,
* testsuite/ld-x86-64/pr19636-2a.d,
* testsuite/ld-x86-64/pr19636-2e.d,
* testsuite/ld-x86-64/pr19636-2f.d,
* testsuite/ld-x86-64/pr19636-3a.d,
* testsuite/ld-x86-64/pr19645.d,
* testsuite/ld-x86-64/pr19807-2b.d,
* testsuite/ld-x86-64/pr19807-2d.d,
* testsuite/ld-x86-64/pr19827-nacl.rd,
* testsuite/ld-x86-64/pr19827.rd,
* testsuite/ld-x86-64/pr20253-4a.d,
* testsuite/ld-x86-64/pr20253-4b.d,
* testsuite/ld-x86-64/pr20253-4d.d,
* testsuite/ld-x86-64/pr20253-4e.d,
* testsuite/ld-x86-64/pr20253-5a.d,
* testsuite/ld-x86-64/pr20253-5b.d,
* testsuite/ld-x86-64/tlsbin-nacl.rd,
* testsuite/ld-x86-64/tlsbin.rd,
* testsuite/ld-x86-64/tlspic-nacl.rd,
* testsuite/ld-x86-64/tlspic.rd,
* testsuite/ld-x86-64/tlspic2-nacl.rd: Update for
pluralization fixes.
* elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
* elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
* elf32-arm.c (elf32_arm_nacl_plt0_entry, elf32_arm_nacl_plt_entry):
New variables.
(struct elf32_arm_link_hash_table): New member `nacl_p'.
(elf32_arm_link_hash_table_create): Initialize it.
(elf32_arm_nacl_link_hash_table_create): New function.
(arm_movw_immediate, arm_movt_immediate): New functions.
(elf32_arm_populate_plt_entry): Test HTAB->nacl_p.
(elf32_arm_finish_dynamic_sections): Likewise.
(elf32_arm_output_plt_map_1): Likewise.
(bfd_elf32_littlearm_nacl_vec, bfd_elf32_bigarm_nacl_vec):
New backend vector stanza.
(elf32_arm_nacl_modify_segment_map): New function.
* config.bfd: Handle arm-*-nacl*, armeb-*-nacl*.
* targets.c: Support bfd_elf32_{big,little}_nacl_vec.
* configure.in: Likewise.
(bfd_elf32_bigarm_nacl_vec): Add elf-nacl.lo here.
(bfd_elf32_littlearm_nacl_vec): Likewise.
(bfd_elf32_bigarm_vec, bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerated.
* configure.tgt (arm-*-nacl*): Match it.
* config/te-nacl.h (FPU_DEFAULT, EABI_DEFAULT): Define.
(LOCAL_LABELS_DOLLAR): Define.
* config/tc-arm.c (elf32_arm_target_format) [TE_NACL]:
Use nacl format variants.
* gas/elf/elf.exp (run_elf_list_test): Treat arm-*-nacl* targets
as -armeabi.
* gas/arm/any-idiv.d: Match *-*-nacl* targets too.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arch4t-eabi.d: Likewise.
* gas/arm/attr-any-armv4t.d: Likewise.
* gas/arm/attr-any-thumbv6.d: Likewise.
* gas/arm/attr-cpu-directive.d: Likewise.
* gas/arm/attr-default.d: Likewise.
* gas/arm/attr-march-all.d: Likewise.
* gas/arm/attr-march-armv1.d: Likewise.
* gas/arm/attr-march-armv2a.d: Likewise.
* gas/arm/attr-march-armv2.d: Likewise.
* gas/arm/attr-march-armv2s.d: Likewise.
* gas/arm/attr-march-armv3.d: Likewise.
* gas/arm/attr-march-armv3m.d: Likewise.
* gas/arm/attr-march-armv4.d: Likewise.
* gas/arm/attr-march-armv4t.d: Likewise.
* gas/arm/attr-march-armv4txm.d: Likewise.
* gas/arm/attr-march-armv4xm.d: Likewise.
* gas/arm/attr-march-armv5.d: Likewise.
* gas/arm/attr-march-armv5t.d: Likewise.
* gas/arm/attr-march-armv5te.d: Likewise.
* gas/arm/attr-march-armv5tej.d: Likewise.
* gas/arm/attr-march-armv5texp.d: Likewise.
* gas/arm/attr-march-armv5txm.d: Likewise.
* gas/arm/attr-march-armv6.d: Likewise.
* gas/arm/attr-march-armv6j.d: Likewise.
* gas/arm/attr-march-armv6k.d: Likewise.
* gas/arm/attr-march-armv6k+sec.d: Likewise.
* gas/arm/attr-march-armv6kt2.d: Likewise.
* gas/arm/attr-march-armv6-m.d: Likewise.
* gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/arm/attr-march-armv6s-m.d: Likewise.
* gas/arm/attr-march-armv6t2.d: Likewise.
* gas/arm/attr-march-armv6z.d: Likewise.
* gas/arm/attr-march-armv6zk.d: Likewise.
* gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/arm/attr-march-armv7-a.d: Likewise.
* gas/arm/attr-march-armv7a.d: Likewise.
* gas/arm/attr-march-armv7-a+idiv.d: Likewise.
* gas/arm/attr-march-armv7-a+mp.d: Likewise.
* gas/arm/attr-march-armv7-a+sec.d: Likewise.
* gas/arm/attr-march-armv7-a+sec+virt.d: Likewise.
* gas/arm/attr-march-armv7-a+virt.d: Likewise.
* gas/arm/attr-march-armv7.d: Likewise.
* gas/arm/attr-march-armv7em.d: Likewise.
* gas/arm/attr-march-armv7-m.d: Likewise.
* gas/arm/attr-march-armv7m.d: Likewise.
* gas/arm/attr-march-armv7-r.d: Likewise.
* gas/arm/attr-march-armv7r.d: Likewise.
* gas/arm/attr-march-armv7-r+mp.d: Likewise.
* gas/arm/attr-march-iwmmxt2.d: Likewise.
* gas/arm/attr-march-iwmmxt.d: Likewise.
* gas/arm/attr-march-xscale.d: Likewise.
* gas/arm/attr-mcpu.d: Likewise.
* gas/arm/attr-mfpu-arm1020e.d: Likewise.
* gas/arm/attr-mfpu-arm1020t.d: Likewise.
* gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
* gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
* gas/arm/attr-mfpu-arm7500fe.d: Likewise.
* gas/arm/attr-mfpu-fpa10.d: Likewise.
* gas/arm/attr-mfpu-fpa11.d: Likewise.
* gas/arm/attr-mfpu-fpa.d: Likewise.
* gas/arm/attr-mfpu-fpe2.d: Likewise.
* gas/arm/attr-mfpu-fpe3.d: Likewise.
* gas/arm/attr-mfpu-fpe.d: Likewise.
* gas/arm/attr-mfpu-maverick.d: Likewise.
* gas/arm/attr-mfpu-neon.d: Likewise.
* gas/arm/attr-mfpu-neon-fp16.d: Likewise.
* gas/arm/attr-mfpu-softfpa.d: Likewise.
* gas/arm/attr-mfpu-softvfp.d: Likewise.
* gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
* gas/arm/attr-mfpu-vfp10.d: Likewise.
* gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
* gas/arm/attr-mfpu-vfp3.d: Likewise.
* gas/arm/attr-mfpu-vfp9.d: Likewise.
* gas/arm/attr-mfpu-vfp.d: Likewise.
* gas/arm/attr-mfpu-vfpv2.d: Likewise.
* gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv3.d: Likewise.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-mfpu-vfpxd.d: Likewise.
* gas/arm/attr-names.d: Likewise.
* gas/arm/attr-order.d: Likewise.
* gas/arm/attr-override-cpu-directive.d: Likewise.
* gas/arm/attr-override-mcpu.d: Likewise.
* gas/arm/got_prel.d: Likewise.
* gas/arm/mapdir.d: Likewise.
* gas/arm/mapmisc.d: Likewise.
* gas/arm/mapsecs.d: Likewise.
* gas/arm/mapshort-eabi.d: Likewise.
* gas/arm/mapshort-elf.d: Likewise.
* gas/arm/mov-highregs-any.d: Likewise.
* gas/arm/mov-lowregs-any.d: Likewise.
* gas/arm/pr12198-1.d: Likewise.
* gas/arm/pr12198-2.d: Likewise.
* gas/arm/thumb.d: Likewise.
* gas/arm/thumb-eabi.d: Likewise.
* gas/arm/thumbrel.d: Likewise.
* configure.tgt (arm*-*-nacl*, arm*b-*-nacl*): Handle them.
* emulparams/armelf_nacl.sh: New file.
* emulparams/armelfb_nacl.sh: New file.
* Makefile.am (ALL_EMULATION_SOURCES): Add earmelf_nacl.c
and earmelfb_nacl.c here.
(earmelf_nacl.c, earmelfb_nacl.c): New targets.
* Makefile.in: Regenerated.
* ld-arm/arm-elf.exp (armelftests): Split out into ...
(armelftests_common, armelftests_nonacl): ... these two.
(armeabitests): Split out into ...
(armeabitests_common, armeabitests_nonacl): ... these two.
Omit _nonacl sets for arm*-*-nacl* targets.
* ld-arm/farcall-mix.d: Don't match exact addresses, only symbolic ones.
* ld-arm/farcall-mix2.d: Likewise.
* ld-arm/farcall-group.d: Likewise.
* ld-arm/tls-gdesc-got.d: Match variant file formats too.
Accept some variation in exact addresses.
* ld-arm/thumb2-b-interwork.d: Match variant file formats too.
Fix regexps not to care about exact addresses where not relevant.
* ld-arm/thumb2-bl-undefweak.d: Match any hex strings, not any
strings of particular exact lengths.
* ld-arm/thumb2-bl-undefweak1.d: Likewise.
* ld-arm/arm-app.r: Match variant file formats too.
* ld-arm/arm-app-abs32.r: Likewise.
* ld-arm/arm-lib.d: Likewise.
* ld-arm/arm-lib.r: Likewise.
* ld-arm/arm-static-app.r: Likewise.
* ld-arm/armv4-bx.d: Likewise.
* ld-arm/data-only-map.d: Likewise.
* ld-arm/group-relocs.d: Likewise.
* ld-arm/jump19.d: Likewise.
* ld-arm/reloc-boundaries.d: Likewise.
* ld-arm/thumb1-bl.d: Likewise.
* ld-arm/thumb2-bl.d: Likewise.
* ld-arm/tls-app.d: Likewise.
* ld-arm/tls-app.r: Likewise.
* ld-arm/tls-gdierelax.d: Likewise.
* ld-arm/tls-gdierelax2.d: Likewise.
* ld-arm/tls-gdlerelax.d: Likewise.
* ld-arm/tls-lib.d: Likewise.
* ld-arm/tls-lib.r: Likewise.
* ld-arm/tls-mixed.r: Likewise.
* ld-arm/vfp11-fix-none.d: Likewise.
* ld-arm/vfp11-fix-scalar.d: Likewise.
* ld-arm/vfp11-fix-vector.d: Likewise.
* ld-arm/arm-static-app.d: Likewise.
Fix regexps not to care about exact number of leading spaces.
* ld-arm/arm-app-abs32.d: Likewise.
* ld-arm/fix-arm1176-off.d: Likewise.
* ld-arm/fix-arm1176-on.d: Likewise.
* ld-arm/arm-elf.exp: Treat nacl targets like eabi targets.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
ld error/warning messages
This patch standardizes messages in ld, to better conform to the GNU
coding standard. Besides issues of capitalization and full-stops,
I've
- Split up help messages for target options, so that adding a new
option does not mean loss of translation for all the others.
- Embedded tabs have been removed, since a user might have tab stops
set at other than 8 char intervals.
- Added missing program name (%P). ld isn't the compiler.
- Put %F and %X first (and removed %X if %F was present). These can
go anywhere, but look silly in the m%Fiddle of a message, and
choosing "%P%F:" in some messages but "%F%P:" in others leads to the
likelihood of duplication in ld.pot. Besides, the colon belongs
with %P.
* emulparams/call_nop.sh, * emulparams/cet.sh,
* emulparams/elf32mcore.sh, * emultempl/aarch64elf.em
* emultempl/aix.em, * emultempl/alphaelf.em, * emultempl/armcoff.em,
* emultempl/armelf.em, * emultempl/avrelf.em, * emultempl/beos.em,
* emultempl/bfin.em, * emultempl/cr16elf.em, * emultempl/elf32.em,
* emultempl/elf-generic.em, * emultempl/hppaelf.em,
* emultempl/linux.em, * emultempl/lnk960.em,
* emultempl/m68hc1xelf.em, * emultempl/m68kcoff.em,
* emultempl/m68kelf.em, * emultempl/metagelf.em,
* emultempl/mipself.em, * emultempl/mmix-elfnmmo.em,
* emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nds32elf.em,
* emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em,
* emultempl/ppc32elf.em, * emultempl/ppc64elf.em,
* emultempl/scoreelf.em, * emultempl/sh64elf.em,
* emultempl/spuelf.em, * emultempl/sunos.em, * emultempl/tic6xdsbt.em,
* emultempl/ticoff.em, * emultempl/v850elf.em, * emultempl/vms.em,
* emultempl/vxworks.em, * emultempl/xtensaelf.em, * ldcref.c,
* ldctor.c, * ldexp.c, * ldfile.c, * ldgram.y, * ldlang.c,
* ldmain.c, * ldmisc.c, * ldwrite.c, * lexsup.c, * mri.c, * pe-dll.c,
* plugin.c: Standardize error/warning messages.
* testsuite/ld-arc/jli-overflow.err,
* testsuite/ld-arm/cmse-implib-errors.out,
* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
* testsuite/ld-arm/cmse-new-wrong-implib.out,
* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
* testsuite/ld-arm/vxworks1-static.d,
* testsuite/ld-cris/tls-err-20x.d, * testsuite/ld-cris/tls-err-29.d,
* testsuite/ld-cris/tls-err-31.d, * testsuite/ld-cris/tls-err-33.d,
* testsuite/ld-cris/tls-err-35.d, * testsuite/ld-cris/tls-err-37.d,
* testsuite/ld-cris/tls-err-39.d, * testsuite/ld-cris/tls-err-41.d,
* testsuite/ld-cris/tls-err-43.d, * testsuite/ld-cris/tls-err-45.d,
* testsuite/ld-cris/tls-err-47.d, * testsuite/ld-cris/tls-err-49.d,
* testsuite/ld-cris/tls-err-51.d, * testsuite/ld-cris/tls-err-67.d,
* testsuite/ld-elf/dwarf2.err, * testsuite/ld-elf/dwarf3.err,
* testsuite/ld-elf/orphan-5.l, * testsuite/ld-elf/orphan-6.l,
* testsuite/ld-i386/vxworks1-static.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
* testsuite/ld-mips-elf/bal-jalx-pic.d,
* testsuite/ld-mips-elf/jal-global-overflow-1.d,
* testsuite/ld-mips-elf/jal-local-overflow-1.d,
* testsuite/ld-mips-elf/mode-change-error-1.d,
* testsuite/ld-mips-elf/unaligned-branch-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
* testsuite/ld-mips-elf/unaligned-branch.d,
* testsuite/ld-mips-elf/unaligned-jalx-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
* testsuite/ld-mips-elf/unaligned-jump.d,
* testsuite/ld-mips-elf/unaligned-ldpc-1.d,
* testsuite/ld-mips-elf/unaligned-lwpc-1.d,
* testsuite/ld-mips-elf/undefined.d,
* testsuite/ld-mips-elf/vxworks1-static.d,
* testsuite/ld-mmix/bpo-20.d, * testsuite/ld-mmix/bpo-20m.d,
* testsuite/ld-mmix/bpo-7.d, * testsuite/ld-mmix/bpo-7m.d,
* testsuite/ld-mmix/bpo-8.d, * testsuite/ld-mmix/bpo-8m.d,
* testsuite/ld-mmix/greg-17.d, * testsuite/ld-mmix/greg-18.d,
* testsuite/ld-mmix/greg-8.d, * testsuite/ld-mmix/greg-9.d,
* testsuite/ld-plugin/plugin-14.d, * testsuite/ld-plugin/plugin-15.d,
* testsuite/ld-plugin/plugin-16.d, * testsuite/ld-plugin/plugin-20.d,
* testsuite/ld-plugin/plugin-21.d, * testsuite/ld-plugin/plugin-22.d,
* testsuite/ld-plugin/plugin-23.d, * testsuite/ld-plugin/plugin-6.d,
* testsuite/ld-plugin/plugin-7.d, * testsuite/ld-plugin/plugin-8.d,
* testsuite/ld-powerpc/aix-weak-3-32.d,
* testsuite/ld-powerpc/aix-weak-3-64.d,
* testsuite/ld-powerpc/vxworks1-static.d,
* testsuite/ld-sh/vxworks1-static.d,
* testsuite/ld-sparc/vxworks1-static.d,
* testsuite/ld-undefined/undefined.exp,
* testsuite/ld-x86-64/pie1.d: Update for changed errors and warnings.
* testsuite/ld-elf/warn1.d, * testsuite/ld-elf/warn2.d: Correct regex.
opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.
bfd/
* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
(bfd_elf32_bigarm_symbian_vec): Likewise.
(bfd_elf32_bigarm_vxworks_vec): Likewise.
(bfd_elf32_littlearm_vec): Likewise.
(bfd_elf32_littlearm_symbian_vec): Likewise.
(bfd_elf32_littlearm_vxworks_vec): Likewise.
* configure: Regenerate.
* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
(elf32_arm_vxworks_bed): Add forward declaration.
(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
(elf32_arm_vxworks_exec_plt0_entry): New table.
(elf32_arm_vxworks_exec_plt_entry): Likewise.
(elf32_arm_vxworks_shared_plt_entry): Likewise.
(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
(reloc_section_p): New function.
(create_got_section): Use RELOC_SECTION.
(elf32_arm_create_dynamic_sections): Likewise. Call
elf_vxworks_create_dynamic_sections for VxWorks targets.
Choose between the two possible values of plt_header_size
and plt_entry_size.
(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
(elf32_arm_abs12_reloc): New function.
(elf32_arm_final_link_relocate): Call it. Allow the creation of
dynamic R_ARM_ABS12 relocs on VxWorks. Use reloc_section_p,
RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION. Initialize the
r_addend fields of relocs. On rela targets, skip any code that
adjusts in-place addends. When using _bfd_link_final_relocate
to perform a final relocation, pass rel->r_addend as the addend
argument.
(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
object, ignore flags that are not standard on VxWorks.
(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
relocs on VxWorks. Use reloc_section_p.
(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
(allocate_dynrelocs): Use RELOC_SIZE. Account for the size of
.rela.plt.unloaded relocs on VxWorks targets.
(elf32_arm_size_dynamic_sections): Use RELOC_SIZE. Check for
.rela.plt.unloaded as well as .rel(a).plt. Add DT_RELA* tags
instead of DT_REL* tags on RELA targets.
(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle VxWorks
PLT entries. Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
and SWAP_RELOC_OUT. Initialize r_addend fields. Handle DT_RELASZ
like DT_RELSZ. Handle the VxWorks form of initial PLT entry.
Correct the .rela.plt.unreloaded symbol indexes.
(elf32_arm_output_symbol_hook): Call the VxWorks version of this
hook on VxWorks targets.
(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
Minor formatting tweak.
(elf32_arm_vxworks_final_write_processing): New function.
(elf_backend_add_symbol_hook): Override for VxWorks and reset
for Symbian.
(elf_backend_final_write_processing): Likewise.
(elf_backend_emit_relocs): Likewise.
(elf_backend_want_plt_sym): Likewise.
(ELF_MAXPAGESIZE): Likewise.
(elf_backend_may_use_rel_p): Minor formatting tweak.
(elf_backend_may_use_rela_p): Likewise.
(elf_backend_default_use_rela_p): Likewise.
(elf_backend_rela_normal): Likewise.
* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.
gas/
* config/tc-arm.c (md_apply_fix): Install a value of zero into a
BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
R_ARM_ABS12 reloc.
(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
relocs, but adjust by md_pcrel_from_section. Create R_ARM_ABS12
relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
gas/testsuite/
* gas/arm/abs12.s, gas/arm/abs12.d: New test.
* gas/arm/pic.d: Skip for *-*-vxworks*...
* gas/arm/pic_vxworks.d: ...use this version instead.
* gas/arm/unwind_vxworks.d: Fix expected output.
ld/
* emulparams/armelf_vxworks.sh: Include vxworks.sh.
(MAXPAGESIZE): Define.
* emulparams/vxworks.sh: Undefine.
* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
* Makefile.in: Regenerate.
ld/testsuite/
* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
* ld-arm/vxworks2-static.sd: New tests.
* ld-arm/arm-elf.exp: Run them.