WIP MachO binutils port assisted by AI
I may consider upstreaming this in the future.
gas, bfd, gold: Rename Arm v8/v9 architecture tags
Rename the Arm AEABI CPU architecture tag constants and macro definitions to include the
profile suffix for A-profile architectures. This makes the naming
consistent with existing v8-R and v8-M tag names, while preserving the
existing numeric tag values.
Update BFD, GAS and Gold usage accordingly, including attribute combination
tables, architecture checks, and mach selection.
Sivan Shani
(May 28, 2026, 11:33 AM UTC)
ef928484
aa5685c0
+136
-136
+2
-2
bfd/archures.c
+2
-2
bfd/archures.c
···
327
327
.#define bfd_mach_arm_6M 20
328
328
.#define bfd_mach_arm_6SM 21
329
329
.#define bfd_mach_arm_7EM 22
330
-
.#define bfd_mach_arm_8 23
330
+
.#define bfd_mach_arm_8A 23
331
331
.#define bfd_mach_arm_8R 24
332
332
.#define bfd_mach_arm_8M_BASE 25
333
333
.#define bfd_mach_arm_8M_MAIN 26
334
334
.#define bfd_mach_arm_8_1M_MAIN 27
335
-
.#define bfd_mach_arm_9 28
335
+
.#define bfd_mach_arm_9A 28
336
336
. bfd_arch_nds32, {* Andes NDS32. *}
337
337
.#define bfd_mach_n1 1
338
338
.#define bfd_mach_n1h 2
+2
-2
bfd/bfd-in2.h
+2
-2
bfd/bfd-in2.h
···
1571
1571
#define bfd_mach_arm_6M 20
1572
1572
#define bfd_mach_arm_6SM 21
1573
1573
#define bfd_mach_arm_7EM 22
1574
-
#define bfd_mach_arm_8 23
1574
+
#define bfd_mach_arm_8A 23
1575
1575
#define bfd_mach_arm_8R 24
1576
1576
#define bfd_mach_arm_8M_BASE 25
1577
1577
#define bfd_mach_arm_8M_MAIN 26
1578
1578
#define bfd_mach_arm_8_1M_MAIN 27
1579
-
#define bfd_mach_arm_9 28
1579
+
#define bfd_mach_arm_9A 28
1580
1580
bfd_arch_nds32, /* Andes NDS32. */
1581
1581
#define bfd_mach_n1 1
1582
1582
#define bfd_mach_n1h 2
+23
-23
bfd/cpu-arm.c
+23
-23
bfd/cpu-arm.c
···
139
139
{ bfd_mach_arm_7, "cortex-a12" },
140
140
{ bfd_mach_arm_7, "cortex-a15" },
141
141
{ bfd_mach_arm_7, "cortex-a17" },
142
-
{ bfd_mach_arm_8, "cortex-a32" },
143
-
{ bfd_mach_arm_8, "cortex-a35" },
144
-
{ bfd_mach_arm_8, "cortex-a53" },
145
-
{ bfd_mach_arm_8, "cortex-a55" },
146
-
{ bfd_mach_arm_8, "cortex-a57" },
147
-
{ bfd_mach_arm_8, "cortex-a72" },
148
-
{ bfd_mach_arm_8, "cortex-a73" },
149
-
{ bfd_mach_arm_8, "cortex-a75" },
150
-
{ bfd_mach_arm_8, "cortex-a76" },
151
-
{ bfd_mach_arm_8, "cortex-a76ae" },
152
-
{ bfd_mach_arm_8, "cortex-a77" },
153
-
{ bfd_mach_arm_8, "cortex-a78" },
154
-
{ bfd_mach_arm_8, "cortex-a78ae" },
155
-
{ bfd_mach_arm_8, "cortex-a78c" },
142
+
{ bfd_mach_arm_8A, "cortex-a32" },
143
+
{ bfd_mach_arm_8A, "cortex-a35" },
144
+
{ bfd_mach_arm_8A, "cortex-a53" },
145
+
{ bfd_mach_arm_8A, "cortex-a55" },
146
+
{ bfd_mach_arm_8A, "cortex-a57" },
147
+
{ bfd_mach_arm_8A, "cortex-a72" },
148
+
{ bfd_mach_arm_8A, "cortex-a73" },
149
+
{ bfd_mach_arm_8A, "cortex-a75" },
150
+
{ bfd_mach_arm_8A, "cortex-a76" },
151
+
{ bfd_mach_arm_8A, "cortex-a76ae" },
152
+
{ bfd_mach_arm_8A, "cortex-a77" },
153
+
{ bfd_mach_arm_8A, "cortex-a78" },
154
+
{ bfd_mach_arm_8A, "cortex-a78ae" },
155
+
{ bfd_mach_arm_8A, "cortex-a78c" },
156
156
{ bfd_mach_arm_6SM, "cortex-m0" },
157
157
{ bfd_mach_arm_6SM, "cortex-m0plus" },
158
158
{ bfd_mach_arm_6SM, "cortex-m1" },
···
166
166
{ bfd_mach_arm_7, "cortex-r4f" },
167
167
{ bfd_mach_arm_7, "cortex-r5" },
168
168
{ bfd_mach_arm_8R, "cortex-r52" },
169
-
{ bfd_mach_arm_8R, "cortex-r52plus" },
169
+
{ bfd_mach_arm_8R, "cortex-r52plus" },
170
170
{ bfd_mach_arm_7, "cortex-r7" },
171
171
{ bfd_mach_arm_7, "cortex-r8" },
172
-
{ bfd_mach_arm_8, "cortex-x1" },
173
-
{ bfd_mach_arm_8, "cortex-x1c" },
172
+
{ bfd_mach_arm_8A, "cortex-x1" },
173
+
{ bfd_mach_arm_8A, "cortex-x1c" },
174
174
{ bfd_mach_arm_4T, "ep9312" },
175
-
{ bfd_mach_arm_8, "exynos-m1" },
175
+
{ bfd_mach_arm_8A, "exynos-m1" },
176
176
{ bfd_mach_arm_4, "fa526" },
177
177
{ bfd_mach_arm_5TE, "fa606te" },
178
178
{ bfd_mach_arm_5TE, "fa616te" },
···
192
192
{ bfd_mach_arm_4, "strongarm1100" },
193
193
{ bfd_mach_arm_4, "strongarm1110" },
194
194
{ bfd_mach_arm_XScale, "xscale" },
195
-
{ bfd_mach_arm_8, "xgene1" },
196
-
{ bfd_mach_arm_8, "xgene2" },
197
-
{ bfd_mach_arm_9, "cortex-a710" },
195
+
{ bfd_mach_arm_8A, "xgene1" },
196
+
{ bfd_mach_arm_8A, "xgene2" },
197
+
{ bfd_mach_arm_9A, "cortex-a710" },
198
198
{ bfd_mach_arm_iWMMXt, "iwmmxt" },
199
199
{ bfd_mach_arm_iWMMXt2, "iwmmxt2" },
200
200
{ bfd_mach_arm_unknown, "arm_any" }
···
262
262
N (bfd_mach_arm_6M, "armv6-m", false, & arch_info_struct[19]),
263
263
N (bfd_mach_arm_6SM, "armv6s-m", false, & arch_info_struct[20]),
264
264
N (bfd_mach_arm_7EM, "armv7e-m", false, & arch_info_struct[21]),
265
-
N (bfd_mach_arm_8, "armv8-a", false, & arch_info_struct[22]),
265
+
N (bfd_mach_arm_8A, "armv8-a", false, & arch_info_struct[22]),
266
266
N (bfd_mach_arm_8R, "armv8-r", false, & arch_info_struct[23]),
267
267
N (bfd_mach_arm_8M_BASE, "armv8-m.base", false, & arch_info_struct[24]),
268
268
N (bfd_mach_arm_8M_MAIN, "armv8-m.main", false, & arch_info_struct[25]),
269
269
N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", false, & arch_info_struct[26]),
270
-
N (bfd_mach_arm_9, "armv9-a", false, & arch_info_struct[27]),
270
+
N (bfd_mach_arm_9A, "armv9-a", false, & arch_info_struct[27]),
271
271
N (bfd_mach_arm_unknown, "arm_any", false, NULL)
272
272
};
273
273
+60
-60
bfd/elf32-arm.c
+60
-60
bfd/elf32-arm.c
···
3876
3876
return (arch == TAG_CPU_ARCH_V6T2
3877
3877
|| arch == TAG_CPU_ARCH_V7
3878
3878
|| arch == TAG_CPU_ARCH_V7E_M
3879
-
|| arch == TAG_CPU_ARCH_V8
3879
+
|| arch == TAG_CPU_ARCH_V8A
3880
3880
|| arch == TAG_CPU_ARCH_V8R
3881
3881
|| arch == TAG_CPU_ARCH_V8M_MAIN
3882
3882
|| arch == TAG_CPU_ARCH_V8_1M_MAIN);
···
3891
3891
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3892
3892
3893
3893
/* Force return logic to be reviewed for each new architecture. */
3894
-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
3894
+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V9A);
3895
3895
3896
3896
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3897
3897
return (arch == TAG_CPU_ARCH_V6T2
···
4032
4032
Tag_CPU_arch);
4033
4033
4034
4034
/* Force return logic to be reviewed for each new architecture. */
4035
-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
4035
+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V9A);
4036
4036
4037
4037
return (arch == TAG_CPU_ARCH_V6T2
4038
4038
|| arch == TAG_CPU_ARCH_V6K
4039
4039
|| arch == TAG_CPU_ARCH_V7
4040
-
|| arch == TAG_CPU_ARCH_V8
4040
+
|| arch == TAG_CPU_ARCH_V8A
4041
4041
|| arch == TAG_CPU_ARCH_V8R
4042
-
|| arch == TAG_CPU_ARCH_V9);
4042
+
|| arch == TAG_CPU_ARCH_V9A);
4043
4043
}
4044
4044
4045
4045
static bool
···
13767
13767
return bfd_mach_arm_6SM;
13768
13768
case TAG_CPU_ARCH_V7E_M:
13769
13769
return bfd_mach_arm_7EM;
13770
-
case TAG_CPU_ARCH_V8:
13771
-
return bfd_mach_arm_8;
13770
+
case TAG_CPU_ARCH_V8A:
13771
+
return bfd_mach_arm_8A;
13772
13772
case TAG_CPU_ARCH_V8R:
13773
13773
return bfd_mach_arm_8R;
13774
13774
case TAG_CPU_ARCH_V8M_BASE:
···
13777
13777
return bfd_mach_arm_8M_MAIN;
13778
13778
case TAG_CPU_ARCH_V8_1M_MAIN:
13779
13779
return bfd_mach_arm_8_1M_MAIN;
13780
-
case TAG_CPU_ARCH_V9:
13781
-
return bfd_mach_arm_9;
13780
+
case TAG_CPU_ARCH_V9A:
13781
+
return bfd_mach_arm_9A;
13782
13782
13783
13783
default:
13784
13784
/* Force entry to be added for any new known Tag_CPU_arch value. */
···
14111
14111
};
14112
14112
static const int v8[] =
14113
14113
{
14114
-
T(V8), /* PRE_V4. */
14115
-
T(V8), /* V4. */
14116
-
T(V8), /* V4T. */
14117
-
T(V8), /* V5T. */
14118
-
T(V8), /* V5TE. */
14119
-
T(V8), /* V5TEJ. */
14120
-
T(V8), /* V6. */
14121
-
T(V8), /* V6KZ. */
14122
-
T(V8), /* V6T2. */
14123
-
T(V8), /* V6K. */
14124
-
T(V8), /* V7. */
14125
-
T(V8), /* V6_M. */
14126
-
T(V8), /* V6S_M. */
14127
-
T(V8), /* V7E_M. */
14128
-
T(V8), /* V8. */
14129
-
T(V8), /* V8-R. */
14130
-
T(V8), /* V8-M.BASE. */
14131
-
T(V8), /* V8-M.MAIN. */
14132
-
T(V8), /* V8.1. */
14133
-
T(V8), /* V8.2. */
14134
-
T(V8), /* V8.3. */
14135
-
T(V8), /* V8.1-M.MAIN. */
14114
+
T(V8A), /* PRE_V4. */
14115
+
T(V8A), /* V4. */
14116
+
T(V8A), /* V4T. */
14117
+
T(V8A), /* V5T. */
14118
+
T(V8A), /* V5TE. */
14119
+
T(V8A), /* V5TEJ. */
14120
+
T(V8A), /* V6. */
14121
+
T(V8A), /* V6KZ. */
14122
+
T(V8A), /* V6T2. */
14123
+
T(V8A), /* V6K. */
14124
+
T(V8A), /* V7. */
14125
+
T(V8A), /* V6_M. */
14126
+
T(V8A), /* V6S_M. */
14127
+
T(V8A), /* V7E_M. */
14128
+
T(V8A), /* V8A. */
14129
+
T(V8A), /* V8-R. */
14130
+
T(V8A), /* V8-M.BASE. */
14131
+
T(V8A), /* V8-M.MAIN. */
14132
+
T(V8A), /* V8.1. */
14133
+
T(V8A), /* V8.2. */
14134
+
T(V8A), /* V8.3. */
14135
+
T(V8A), /* V8.1-M.MAIN. */
14136
14136
};
14137
14137
static const int v8r[] =
14138
14138
{
···
14150
14150
T(V8R), /* V6_M. */
14151
14151
T(V8R), /* V6S_M. */
14152
14152
T(V8R), /* V7E_M. */
14153
-
T(V8), /* V8. */
14153
+
T(V8A), /* V8A. */
14154
14154
T(V8R), /* V8R. */
14155
14155
};
14156
14156
static const int v8m_baseline[] =
···
14169
14169
T(V8M_BASE), /* V6_M. */
14170
14170
T(V8M_BASE), /* V6S_M. */
14171
14171
-1, /* V7E_M. */
14172
-
-1, /* V8. */
14172
+
-1, /* V8A. */
14173
14173
-1, /* V8R. */
14174
14174
T(V8M_BASE) /* V8-M BASELINE. */
14175
14175
};
···
14189
14189
T(V8M_MAIN), /* V6_M. */
14190
14190
T(V8M_MAIN), /* V6S_M. */
14191
14191
T(V8M_MAIN), /* V7E_M. */
14192
-
-1, /* V8. */
14192
+
-1, /* V8A. */
14193
14193
-1, /* V8R. */
14194
14194
T(V8M_MAIN), /* V8-M BASELINE. */
14195
14195
T(V8M_MAIN) /* V8-M MAINLINE. */
···
14210
14210
T(V8_1M_MAIN), /* V6_M. */
14211
14211
T(V8_1M_MAIN), /* V6S_M. */
14212
14212
T(V8_1M_MAIN), /* V7E_M. */
14213
-
-1, /* V8. */
14213
+
-1, /* V8A. */
14214
14214
-1, /* V8R. */
14215
14215
T(V8_1M_MAIN), /* V8-M BASELINE. */
14216
14216
T(V8_1M_MAIN), /* V8-M MAINLINE. */
···
14221
14221
};
14222
14222
static const int v9[] =
14223
14223
{
14224
-
T(V9), /* PRE_V4. */
14225
-
T(V9), /* V4. */
14226
-
T(V9), /* V4T. */
14227
-
T(V9), /* V5T. */
14228
-
T(V9), /* V5TE. */
14229
-
T(V9), /* V5TEJ. */
14230
-
T(V9), /* V6. */
14231
-
T(V9), /* V6KZ. */
14232
-
T(V9), /* V6T2. */
14233
-
T(V9), /* V6K. */
14234
-
T(V9), /* V7. */
14235
-
T(V9), /* V6_M. */
14236
-
T(V9), /* V6S_M. */
14237
-
T(V9), /* V7E_M. */
14238
-
T(V9), /* V8. */
14239
-
T(V9), /* V8-R. */
14240
-
T(V9), /* V8-M.BASE. */
14241
-
T(V9), /* V8-M.MAIN. */
14242
-
T(V9), /* V8.1. */
14243
-
T(V9), /* V8.2. */
14244
-
T(V9), /* V8.3. */
14245
-
T(V9), /* V8.1-M.MAIN. */
14246
-
T(V9), /* V9. */
14224
+
T(V9A), /* PRE_V4. */
14225
+
T(V9A), /* V4. */
14226
+
T(V9A), /* V4T. */
14227
+
T(V9A), /* V5T. */
14228
+
T(V9A), /* V5TE. */
14229
+
T(V9A), /* V5TEJ. */
14230
+
T(V9A), /* V6. */
14231
+
T(V9A), /* V6KZ. */
14232
+
T(V9A), /* V6T2. */
14233
+
T(V9A), /* V6K. */
14234
+
T(V9A), /* V7. */
14235
+
T(V9A), /* V6_M. */
14236
+
T(V9A), /* V6S_M. */
14237
+
T(V9A), /* V7E_M. */
14238
+
T(V9A), /* V8A. */
14239
+
T(V9A), /* V8-R. */
14240
+
T(V9A), /* V8-M.BASE. */
14241
+
T(V9A), /* V8-M.MAIN. */
14242
+
T(V9A), /* V8.1. */
14243
+
T(V9A), /* V8.2. */
14244
+
T(V9A), /* V8.3. */
14245
+
T(V9A), /* V8.1-M.MAIN. */
14246
+
T(V9A), /* V9A. */
14247
14247
};
14248
14248
static const int v4t_plus_v6_m[] =
14249
14249
{
···
14261
14261
T(V6_M), /* V6_M. */
14262
14262
T(V6S_M), /* V6S_M. */
14263
14263
T(V7E_M), /* V7E_M. */
14264
-
T(V8), /* V8. */
14264
+
T(V8A), /* V8A. */
14265
14265
-1, /* V8R. */
14266
14266
T(V8M_BASE), /* V8-M BASELINE. */
14267
14267
T(V8M_MAIN), /* V8-M MAINLINE. */
···
14269
14269
-1, /* Unused (19). */
14270
14270
-1, /* Unused (20). */
14271
14271
T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
14272
-
T(V9), /* V9. */
14272
+
T(V9A), /* V9A. */
14273
14273
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14274
14274
};
14275
14275
static const int *const comb[] =
+6
-6
elfcpp/arm.h
+6
-6
elfcpp/arm.h
···
253
253
TAG_CPU_ARCH_V6_M,
254
254
TAG_CPU_ARCH_V6S_M,
255
255
TAG_CPU_ARCH_V7E_M,
256
-
TAG_CPU_ARCH_V8,
256
+
TAG_CPU_ARCH_V8A,
257
257
TAG_CPU_ARCH_V8R,
258
258
TAG_CPU_ARCH_V8M_BASE,
259
259
TAG_CPU_ARCH_V8M_MAIN,
260
-
TAG_CPU_ARCH_8_1A,
261
-
TAG_CPU_ARCH_8_2A,
262
-
TAG_CPU_ARCH_8_3A,
260
+
TAG_CPU_ARCH_V8_1A,
261
+
TAG_CPU_ARCH_V8_2A,
262
+
TAG_CPU_ARCH_V8_3A,
263
263
TAG_CPU_ARCH_V8_1M_MAIN,
264
-
TAG_CPU_ARCH_V9,
265
-
MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V9,
264
+
TAG_CPU_ARCH_V9A,
265
+
MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V9A,
266
266
// Pseudo-architecture to allow objects to be compatible with the subset of
267
267
// armv4t and armv6-m. This value should never be stored in object files.
268
268
TAG_CPU_ARCH_V4T_PLUS_V6_M = (MAX_TAG_CPU_ARCH + 1)
+19
-19
gas/config/tc-arm.c
+19
-19
gas/config/tc-arm.c
···
32100
32100
{TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
32101
32101
{TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
32102
32102
{TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
32103
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
32104
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
32105
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
32106
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
32103
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8A},
32104
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_1A},
32105
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_2A},
32106
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_3A},
32107
32107
{TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
32108
32108
{TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
32109
32109
{TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
32110
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
32111
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
32110
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_4A},
32111
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_5A},
32112
32112
{TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
32113
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_6A},
32114
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_7A},
32115
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_8A},
32116
-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_9A},
32117
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9A},
32118
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9_1A},
32119
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9_2A},
32120
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9_3A},
32121
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9_4A},
32122
-
{TAG_CPU_ARCH_V9, ARM_ARCH_V9_5A},
32113
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_6A},
32114
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_7A},
32115
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_8A},
32116
+
{TAG_CPU_ARCH_V8A, ARM_ARCH_V8_9A},
32117
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9A},
32118
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9_1A},
32119
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9_2A},
32120
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9_3A},
32121
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9_4A},
32122
+
{TAG_CPU_ARCH_V9A, ARM_ARCH_V9_5A},
32123
32123
{-1, ARM_ARCH_NONE}
32124
32124
};
32125
32125
···
32207
32207
if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
32208
32208
{
32209
32209
/* Force revisiting of decision for each new architecture. */
32210
-
gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V9);
32210
+
gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V9A);
32211
32211
*profile = 'A';
32212
-
return TAG_CPU_ARCH_V9;
32212
+
return TAG_CPU_ARCH_V9A;
32213
32213
}
32214
32214
32215
32215
ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
···
32485
32485
by the base architecture.
32486
32486
32487
32487
For new architectures we will have to check these tests. */
32488
-
gas_assert (arch <= TAG_CPU_ARCH_V9);
32488
+
gas_assert (arch <= TAG_CPU_ARCH_V9A);
32489
32489
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
32490
32490
|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
32491
32491
aeabi_set_attribute_int (Tag_DIV_use, 0);
+16
-16
gold/arm.cc
+16
-16
gold/arm.cc
···
11065
11065
};
11066
11066
static const int v8[] =
11067
11067
{
11068
-
T(V8), // PRE_V4.
11069
-
T(V8), // V4.
11070
-
T(V8), // V4T.
11071
-
T(V8), // V5T.
11072
-
T(V8), // V5TE.
11073
-
T(V8), // V5TEJ.
11074
-
T(V8), // V6.
11075
-
T(V8), // V6KZ.
11076
-
T(V8), // V6T2.
11077
-
T(V8), // V6K.
11078
-
T(V8), // V7.
11079
-
T(V8), // V6_M.
11080
-
T(V8), // V6S_M.
11081
-
T(V8), // V7E_M.
11082
-
T(V8) // V8.
11068
+
T(V8A), // PRE_V4.
11069
+
T(V8A), // V4.
11070
+
T(V8A), // V4T.
11071
+
T(V8A), // V5T.
11072
+
T(V8A), // V5TE.
11073
+
T(V8A), // V5TEJ.
11074
+
T(V8A), // V6.
11075
+
T(V8A), // V6KZ.
11076
+
T(V8A), // V6T2.
11077
+
T(V8A), // V6K.
11078
+
T(V8A), // V7.
11079
+
T(V8A), // V6_M.
11080
+
T(V8A), // V6S_M.
11081
+
T(V8A), // V7E_M.
11082
+
T(V8A) // V8.
11083
11083
};
11084
11084
static const int v4t_plus_v6_m[] =
11085
11085
{
···
11097
11097
T(V6_M), // V6_M.
11098
11098
T(V6S_M), // V6S_M.
11099
11099
T(V7E_M), // V7E_M.
11100
-
T(V8), // V8.
11100
+
T(V8A), // V8.
11101
11101
T(V4T_PLUS_V6_M) // V4T plus V6_M.
11102
11102
};
11103
11103
static const int* comb[] =
+6
-6
include/elf/arm.h
+6
-6
include/elf/arm.h
···
108
108
#define TAG_CPU_ARCH_V6_M 11
109
109
#define TAG_CPU_ARCH_V6S_M 12
110
110
#define TAG_CPU_ARCH_V7E_M 13
111
-
#define TAG_CPU_ARCH_V8 14
111
+
#define TAG_CPU_ARCH_V8A 14
112
112
#define TAG_CPU_ARCH_V8R 15
113
113
#define TAG_CPU_ARCH_V8M_BASE 16
114
114
#define TAG_CPU_ARCH_V8M_MAIN 17
115
-
#define TAG_CPU_ARCH_8_1A 18
116
-
#define TAG_CPU_ARCH_8_2A 19
117
-
#define TAG_CPU_ARCH_8_3A 20
115
+
#define TAG_CPU_ARCH_V8_1A 18
116
+
#define TAG_CPU_ARCH_V8_2A 19
117
+
#define TAG_CPU_ARCH_V8_3A 20
118
118
#define TAG_CPU_ARCH_V8_1M_MAIN 21
119
-
#define TAG_CPU_ARCH_V9 22
120
-
#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V9
119
+
#define TAG_CPU_ARCH_V9A 22
120
+
#define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V9A
121
121
/* Pseudo-architecture to allow objects to be compatible with the subset of
122
122
armv4t and armv6-m. This value should never be stored in object files. */
123
123
#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
+2
-2
opcodes/arm-dis.c
+2
-2
opcodes/arm-dis.c
···
12301
12301
case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12302
12302
case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12303
12303
case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12304
-
case bfd_mach_arm_8:
12304
+
case bfd_mach_arm_8A:
12305
12305
{
12306
12306
/* Add bits for extensions that Armv8.6-A recognizes. */
12307
12307
arm_feature_set armv8_6_ext_fset
···
12320
12320
ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12321
12321
force_thumb = 1;
12322
12322
break;
12323
-
case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12323
+
case bfd_mach_arm_9A: ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12324
12324
/* If the machine type is unknown allow all architecture types and all
12325
12325
extensions, with the exception of MVE as that clashes with NEON. */
12326
12326
case bfd_mach_arm_unknown: