theoparis.com / binutils-apple
WIP MachO binutils port assisted by AI I may consider upstreaming this in the future.
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sim: mips: migrate to standard uintXX_t types

Move off the sim-specific unsignedXX types and to the standard uintXX_t
types that C11 provides.

Mike Frysinger (Jan 6, 2022, 1:17 AM EST) b331e677 2875d098

+1083 -1083
+126 -126
sim/mips/cp1.c
··· 90 90 /* Extract packed single values: */ 91 91 #define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF) 92 92 #define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF) 93 - #define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \ 94 - | (unsigned64)((l) & 0xFFFFFFFF)) 93 + #define FP_PS_cat(u,l) (((uint64_t)((u) & (unsigned)0xFFFFFFFF) << 32) \ 94 + | (uint64_t)((l) & 0xFFFFFFFF)) 95 95 96 96 /* Explicit QNaN values. */ 97 97 #define FPQNaN_SINGLE (0x7FBFFFFF) ··· 360 360 address_word cia, 361 361 int fcr) 362 362 { 363 - unsigned32 value = 0; 363 + uint32_t value = 0; 364 364 365 365 switch (fcr) 366 366 { ··· 393 393 int fcr, 394 394 unsigned_word value) 395 395 { 396 - unsigned32 v; 396 + uint32_t v; 397 397 398 398 v = VL4_8(value); 399 399 switch (fcr) ··· 523 523 /* Comparison operations. */ 524 524 525 525 static sim_fpu_status 526 - fp_test(unsigned64 op1, 527 - unsigned64 op2, 526 + fp_test(uint64_t op1, 527 + uint64_t op2, 528 528 FP_formats fmt, 529 529 int abs, 530 530 int cond, ··· 584 584 void 585 585 fp_cmp(sim_cpu *cpu, 586 586 address_word cia, 587 - unsigned64 op1, 588 - unsigned64 op2, 587 + uint64_t op1, 588 + uint64_t op2, 589 589 FP_formats fmt, 590 590 int abs, 591 591 int cond, ··· 628 628 629 629 /* Basic arithmetic operations. */ 630 630 631 - static unsigned64 631 + static uint64_t 632 632 fp_unary(sim_cpu *cpu, 633 633 address_word cia, 634 634 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *), 635 - unsigned64 op, 635 + uint64_t op, 636 636 FP_formats fmt) 637 637 { 638 638 sim_fpu wop; ··· 640 640 sim_fpu_round round = rounding_mode (GETRM()); 641 641 sim_fpu_denorm denorm = denorm_mode (cpu); 642 642 sim_fpu_status status = 0; 643 - unsigned64 result = 0; 643 + uint64_t result = 0; 644 644 645 645 /* The format type has already been checked: */ 646 646 switch (fmt) 647 647 { 648 648 case fmt_single: 649 649 { 650 - unsigned32 res; 650 + uint32_t res; 651 651 sim_fpu_32to (&wop, op); 652 652 status |= (*sim_fpu_op) (&ans, &wop); 653 653 status |= sim_fpu_round_32 (&ans, round, denorm); ··· 657 657 } 658 658 case fmt_double: 659 659 { 660 - unsigned64 res; 660 + uint64_t res; 661 661 sim_fpu_64to (&wop, op); 662 662 status |= (*sim_fpu_op) (&ans, &wop); 663 663 status |= sim_fpu_round_64 (&ans, round, denorm); ··· 668 668 case fmt_ps: 669 669 { 670 670 int status_u = 0, status_l = 0; 671 - unsigned32 res_u, res_l; 671 + uint32_t res_u, res_l; 672 672 sim_fpu_32to (&wop, FP_PS_upper(op)); 673 673 status_u |= (*sim_fpu_op) (&ans, &wop); 674 674 sim_fpu_to32 (&res_u, &ans); ··· 688 688 return result; 689 689 } 690 690 691 - static unsigned64 691 + static uint64_t 692 692 fp_binary(sim_cpu *cpu, 693 693 address_word cia, 694 694 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), 695 - unsigned64 op1, 696 - unsigned64 op2, 695 + uint64_t op1, 696 + uint64_t op2, 697 697 FP_formats fmt) 698 698 { 699 699 sim_fpu wop1; ··· 702 702 sim_fpu_round round = rounding_mode (GETRM()); 703 703 sim_fpu_denorm denorm = denorm_mode (cpu); 704 704 sim_fpu_status status = 0; 705 - unsigned64 result = 0; 705 + uint64_t result = 0; 706 706 707 707 /* The format type has already been checked: */ 708 708 switch (fmt) 709 709 { 710 710 case fmt_single: 711 711 { 712 - unsigned32 res; 712 + uint32_t res; 713 713 sim_fpu_32to (&wop1, op1); 714 714 sim_fpu_32to (&wop2, op2); 715 715 status |= (*sim_fpu_op) (&ans, &wop1, &wop2); ··· 720 720 } 721 721 case fmt_double: 722 722 { 723 - unsigned64 res; 723 + uint64_t res; 724 724 sim_fpu_64to (&wop1, op1); 725 725 sim_fpu_64to (&wop2, op2); 726 726 status |= (*sim_fpu_op) (&ans, &wop1, &wop2); ··· 732 732 case fmt_ps: 733 733 { 734 734 int status_u = 0, status_l = 0; 735 - unsigned32 res_u, res_l; 735 + uint32_t res_u, res_l; 736 736 sim_fpu_32to (&wop1, FP_PS_upper(op1)); 737 737 sim_fpu_32to (&wop2, FP_PS_upper(op2)); 738 738 status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2); ··· 757 757 /* Common MAC code for single operands (.s or .d), defers setting FCSR. */ 758 758 static sim_fpu_status 759 759 inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), 760 - unsigned64 op1, 761 - unsigned64 op2, 762 - unsigned64 op3, 760 + uint64_t op1, 761 + uint64_t op2, 762 + uint64_t op3, 763 763 int scale, 764 764 int negate, 765 765 FP_formats fmt, 766 766 sim_fpu_round round, 767 767 sim_fpu_denorm denorm, 768 - unsigned64 *result) 768 + uint64_t *result) 769 769 { 770 770 sim_fpu wop1; 771 771 sim_fpu wop2; 772 772 sim_fpu ans; 773 773 sim_fpu_status status = 0; 774 774 sim_fpu_status op_status; 775 - unsigned64 temp = 0; 775 + uint64_t temp = 0; 776 776 777 777 switch (fmt) 778 778 { 779 779 case fmt_single: 780 780 { 781 - unsigned32 res; 781 + uint32_t res; 782 782 sim_fpu_32to (&wop1, op1); 783 783 sim_fpu_32to (&wop2, op2); 784 784 status |= sim_fpu_mul (&ans, &wop1, &wop2); ··· 804 804 } 805 805 case fmt_double: 806 806 { 807 - unsigned64 res; 807 + uint64_t res; 808 808 sim_fpu_64to (&wop1, op1); 809 809 sim_fpu_64to (&wop2, op2); 810 810 status |= sim_fpu_mul (&ans, &wop1, &wop2); ··· 842 842 argument is an adjustment to the exponent of the intermediate 843 843 product op1*op2. It is currently non-zero for rsqrt2 (-1), which 844 844 requires an effective division by 2. */ 845 - static unsigned64 845 + static uint64_t 846 846 fp_mac(sim_cpu *cpu, 847 847 address_word cia, 848 848 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), 849 - unsigned64 op1, 850 - unsigned64 op2, 851 - unsigned64 op3, 849 + uint64_t op1, 850 + uint64_t op2, 851 + uint64_t op3, 852 852 int scale, 853 853 int negate, 854 854 FP_formats fmt) ··· 856 856 sim_fpu_round round = rounding_mode (GETRM()); 857 857 sim_fpu_denorm denorm = denorm_mode (cpu); 858 858 sim_fpu_status status = 0; 859 - unsigned64 result = 0; 859 + uint64_t result = 0; 860 860 861 861 /* The format type has already been checked: */ 862 862 switch (fmt) ··· 869 869 case fmt_ps: 870 870 { 871 871 int status_u, status_l; 872 - unsigned64 result_u, result_l; 872 + uint64_t result_u, result_l; 873 873 status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2), 874 874 FP_PS_upper(op3), scale, negate, fmt_single, 875 875 round, denorm, &result_u); ··· 891 891 892 892 /* Common rsqrt code for single operands (.s or .d), intermediate rounding. */ 893 893 static sim_fpu_status 894 - inner_rsqrt(unsigned64 op1, 894 + inner_rsqrt(uint64_t op1, 895 895 FP_formats fmt, 896 896 sim_fpu_round round, 897 897 sim_fpu_denorm denorm, 898 - unsigned64 *result) 898 + uint64_t *result) 899 899 { 900 900 sim_fpu wop1; 901 901 sim_fpu ans; 902 902 sim_fpu_status status = 0; 903 903 sim_fpu_status op_status; 904 - unsigned64 temp = 0; 904 + uint64_t temp = 0; 905 905 906 906 switch (fmt) 907 907 { 908 908 case fmt_single: 909 909 { 910 - unsigned32 res; 910 + uint32_t res; 911 911 sim_fpu_32to (&wop1, op1); 912 912 status |= sim_fpu_sqrt (&ans, &wop1); 913 913 status |= sim_fpu_round_32 (&ans, status, round); ··· 921 921 } 922 922 case fmt_double: 923 923 { 924 - unsigned64 res; 924 + uint64_t res; 925 925 sim_fpu_64to (&wop1, op1); 926 926 status |= sim_fpu_sqrt (&ans, &wop1); 927 927 status |= sim_fpu_round_64 (&ans, round, denorm); ··· 941 941 return status; 942 942 } 943 943 944 - static unsigned64 944 + static uint64_t 945 945 fp_inv_sqrt(sim_cpu *cpu, 946 946 address_word cia, 947 - unsigned64 op1, 947 + uint64_t op1, 948 948 FP_formats fmt) 949 949 { 950 950 sim_fpu_round round = rounding_mode (GETRM()); 951 951 sim_fpu_round denorm = denorm_mode (cpu); 952 952 sim_fpu_status status = 0; 953 - unsigned64 result = 0; 953 + uint64_t result = 0; 954 954 955 955 /* The format type has already been checked: */ 956 956 switch (fmt) ··· 962 962 case fmt_ps: 963 963 { 964 964 int status_u, status_l; 965 - unsigned64 result_u, result_l; 965 + uint64_t result_u, result_l; 966 966 status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm, 967 967 &result_u); 968 968 status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm, ··· 981 981 } 982 982 983 983 984 - unsigned64 984 + uint64_t 985 985 fp_abs(sim_cpu *cpu, 986 986 address_word cia, 987 - unsigned64 op, 987 + uint64_t op, 988 988 FP_formats fmt) 989 989 { 990 990 return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt); 991 991 } 992 992 993 - unsigned64 993 + uint64_t 994 994 fp_neg(sim_cpu *cpu, 995 995 address_word cia, 996 - unsigned64 op, 996 + uint64_t op, 997 997 FP_formats fmt) 998 998 { 999 999 return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt); 1000 1000 } 1001 1001 1002 - unsigned64 1002 + uint64_t 1003 1003 fp_add(sim_cpu *cpu, 1004 1004 address_word cia, 1005 - unsigned64 op1, 1006 - unsigned64 op2, 1005 + uint64_t op1, 1006 + uint64_t op2, 1007 1007 FP_formats fmt) 1008 1008 { 1009 1009 return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt); 1010 1010 } 1011 1011 1012 - unsigned64 1012 + uint64_t 1013 1013 fp_sub(sim_cpu *cpu, 1014 1014 address_word cia, 1015 - unsigned64 op1, 1016 - unsigned64 op2, 1015 + uint64_t op1, 1016 + uint64_t op2, 1017 1017 FP_formats fmt) 1018 1018 { 1019 1019 return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt); 1020 1020 } 1021 1021 1022 - unsigned64 1022 + uint64_t 1023 1023 fp_mul(sim_cpu *cpu, 1024 1024 address_word cia, 1025 - unsigned64 op1, 1026 - unsigned64 op2, 1025 + uint64_t op1, 1026 + uint64_t op2, 1027 1027 FP_formats fmt) 1028 1028 { 1029 1029 return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt); 1030 1030 } 1031 1031 1032 - unsigned64 1032 + uint64_t 1033 1033 fp_div(sim_cpu *cpu, 1034 1034 address_word cia, 1035 - unsigned64 op1, 1036 - unsigned64 op2, 1035 + uint64_t op1, 1036 + uint64_t op2, 1037 1037 FP_formats fmt) 1038 1038 { 1039 1039 return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt); 1040 1040 } 1041 1041 1042 - unsigned64 1042 + uint64_t 1043 1043 fp_recip(sim_cpu *cpu, 1044 1044 address_word cia, 1045 - unsigned64 op, 1045 + uint64_t op, 1046 1046 FP_formats fmt) 1047 1047 { 1048 1048 return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt); 1049 1049 } 1050 1050 1051 - unsigned64 1051 + uint64_t 1052 1052 fp_sqrt(sim_cpu *cpu, 1053 1053 address_word cia, 1054 - unsigned64 op, 1054 + uint64_t op, 1055 1055 FP_formats fmt) 1056 1056 { 1057 1057 return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt); 1058 1058 } 1059 1059 1060 - unsigned64 1060 + uint64_t 1061 1061 fp_rsqrt(sim_cpu *cpu, 1062 1062 address_word cia, 1063 - unsigned64 op, 1063 + uint64_t op, 1064 1064 FP_formats fmt) 1065 1065 { 1066 1066 return fp_inv_sqrt(cpu, cia, op, fmt); 1067 1067 } 1068 1068 1069 - unsigned64 1069 + uint64_t 1070 1070 fp_madd(sim_cpu *cpu, 1071 1071 address_word cia, 1072 - unsigned64 op1, 1073 - unsigned64 op2, 1074 - unsigned64 op3, 1072 + uint64_t op1, 1073 + uint64_t op2, 1074 + uint64_t op3, 1075 1075 FP_formats fmt) 1076 1076 { 1077 1077 return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt); 1078 1078 } 1079 1079 1080 - unsigned64 1080 + uint64_t 1081 1081 fp_msub(sim_cpu *cpu, 1082 1082 address_word cia, 1083 - unsigned64 op1, 1084 - unsigned64 op2, 1085 - unsigned64 op3, 1083 + uint64_t op1, 1084 + uint64_t op2, 1085 + uint64_t op3, 1086 1086 FP_formats fmt) 1087 1087 { 1088 1088 return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt); 1089 1089 } 1090 1090 1091 - unsigned64 1091 + uint64_t 1092 1092 fp_nmadd(sim_cpu *cpu, 1093 1093 address_word cia, 1094 - unsigned64 op1, 1095 - unsigned64 op2, 1096 - unsigned64 op3, 1094 + uint64_t op1, 1095 + uint64_t op2, 1096 + uint64_t op3, 1097 1097 FP_formats fmt) 1098 1098 { 1099 1099 return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt); 1100 1100 } 1101 1101 1102 - unsigned64 1102 + uint64_t 1103 1103 fp_nmsub(sim_cpu *cpu, 1104 1104 address_word cia, 1105 - unsigned64 op1, 1106 - unsigned64 op2, 1107 - unsigned64 op3, 1105 + uint64_t op1, 1106 + uint64_t op2, 1107 + uint64_t op3, 1108 1108 FP_formats fmt) 1109 1109 { 1110 1110 return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt); ··· 1114 1114 /* MIPS-3D ASE operations. */ 1115 1115 1116 1116 /* Variant of fp_binary for *r.ps MIPS-3D operations. */ 1117 - static unsigned64 1117 + static uint64_t 1118 1118 fp_binary_r(sim_cpu *cpu, 1119 1119 address_word cia, 1120 1120 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *), 1121 - unsigned64 op1, 1122 - unsigned64 op2) 1121 + uint64_t op1, 1122 + uint64_t op2) 1123 1123 { 1124 1124 sim_fpu wop1; 1125 1125 sim_fpu wop2; ··· 1127 1127 sim_fpu_round round = rounding_mode (GETRM ()); 1128 1128 sim_fpu_denorm denorm = denorm_mode (cpu); 1129 1129 sim_fpu_status status_u, status_l; 1130 - unsigned64 result; 1131 - unsigned32 res_u, res_l; 1130 + uint64_t result; 1131 + uint32_t res_u, res_l; 1132 1132 1133 1133 /* The format must be fmt_ps. */ 1134 1134 status_u = 0; ··· 1149 1149 return result; 1150 1150 } 1151 1151 1152 - unsigned64 1152 + uint64_t 1153 1153 fp_add_r(sim_cpu *cpu, 1154 1154 address_word cia, 1155 - unsigned64 op1, 1156 - unsigned64 op2, 1155 + uint64_t op1, 1156 + uint64_t op2, 1157 1157 FP_formats fmt) 1158 1158 { 1159 1159 return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2); 1160 1160 } 1161 1161 1162 - unsigned64 1162 + uint64_t 1163 1163 fp_mul_r(sim_cpu *cpu, 1164 1164 address_word cia, 1165 - unsigned64 op1, 1166 - unsigned64 op2, 1165 + uint64_t op1, 1166 + uint64_t op2, 1167 1167 FP_formats fmt) 1168 1168 { 1169 1169 return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2); ··· 1221 1221 return fpu_inv1 (f, l); 1222 1222 } 1223 1223 1224 - unsigned64 1224 + uint64_t 1225 1225 fp_recip1(sim_cpu *cpu, 1226 1226 address_word cia, 1227 - unsigned64 op, 1227 + uint64_t op, 1228 1228 FP_formats fmt) 1229 1229 { 1230 1230 switch (fmt) ··· 1238 1238 return 0; 1239 1239 } 1240 1240 1241 - unsigned64 1241 + uint64_t 1242 1242 fp_recip2(sim_cpu *cpu, 1243 1243 address_word cia, 1244 - unsigned64 op1, 1245 - unsigned64 op2, 1244 + uint64_t op1, 1245 + uint64_t op2, 1246 1246 FP_formats fmt) 1247 1247 { 1248 - static const unsigned64 one_single = UNSIGNED64 (0x3F800000); 1249 - static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000); 1250 - static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000)); 1251 - unsigned64 one; 1248 + static const uint64_t one_single = UNSIGNED64 (0x3F800000); 1249 + static const uint64_t one_double = UNSIGNED64 (0x3FF0000000000000); 1250 + static const uint64_t one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000)); 1251 + uint64_t one; 1252 1252 1253 1253 /* Implemented as nmsub fd, 1, fs, ft. */ 1254 1254 switch (fmt) ··· 1319 1319 return fpu_inv_sqrt1 (f, l); 1320 1320 } 1321 1321 1322 - unsigned64 1322 + uint64_t 1323 1323 fp_rsqrt1(sim_cpu *cpu, 1324 1324 address_word cia, 1325 - unsigned64 op, 1325 + uint64_t op, 1326 1326 FP_formats fmt) 1327 1327 { 1328 1328 switch (fmt) ··· 1336 1336 return 0; 1337 1337 } 1338 1338 1339 - unsigned64 1339 + uint64_t 1340 1340 fp_rsqrt2(sim_cpu *cpu, 1341 1341 address_word cia, 1342 - unsigned64 op1, 1343 - unsigned64 op2, 1342 + uint64_t op1, 1343 + uint64_t op2, 1344 1344 FP_formats fmt) 1345 1345 { 1346 - static const unsigned64 half_single = UNSIGNED64 (0x3F000000); 1347 - static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000); 1348 - static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000)); 1349 - unsigned64 half; 1346 + static const uint64_t half_single = UNSIGNED64 (0x3F000000); 1347 + static const uint64_t half_double = UNSIGNED64 (0x3FE0000000000000); 1348 + static const uint64_t half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000)); 1349 + uint64_t half; 1350 1350 1351 1351 /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is 1352 1352 done by scaling the exponent during multiply. */ ··· 1374 1374 sim_fpu wop; 1375 1375 sim_fpu_round round = rounding_mode (rm); 1376 1376 sim_fpu_denorm denorm = denorm_mode (cpu); 1377 - unsigned32 result32; 1378 - unsigned64 result64; 1377 + uint32_t result32; 1378 + uint64_t result64; 1379 1379 sim_fpu_status status = 0; 1380 1380 1381 1381 /* Convert the input to sim_fpu internal format */ ··· 1438 1438 return result64; 1439 1439 } 1440 1440 1441 - unsigned64 1441 + uint64_t 1442 1442 ps_lower(sim_cpu *cpu, 1443 1443 address_word cia, 1444 - unsigned64 op) 1444 + uint64_t op) 1445 1445 { 1446 1446 return FP_PS_lower (op); 1447 1447 } 1448 1448 1449 - unsigned64 1449 + uint64_t 1450 1450 ps_upper(sim_cpu *cpu, 1451 1451 address_word cia, 1452 - unsigned64 op) 1452 + uint64_t op) 1453 1453 { 1454 1454 return FP_PS_upper(op); 1455 1455 } 1456 1456 1457 - unsigned64 1457 + uint64_t 1458 1458 pack_ps(sim_cpu *cpu, 1459 1459 address_word cia, 1460 - unsigned64 op1, 1461 - unsigned64 op2, 1460 + uint64_t op1, 1461 + uint64_t op2, 1462 1462 FP_formats fmt) 1463 1463 { 1464 - unsigned64 result = 0; 1464 + uint64_t result = 0; 1465 1465 1466 1466 /* The registers must specify FPRs valid for operands of type 1467 1467 "fmt". If they are not valid, the result is undefined. */ ··· 1472 1472 case fmt_single: 1473 1473 { 1474 1474 sim_fpu wop; 1475 - unsigned32 res_u, res_l; 1475 + uint32_t res_u, res_l; 1476 1476 sim_fpu_32to (&wop, op1); 1477 1477 sim_fpu_to32 (&res_u, &wop); 1478 1478 sim_fpu_32to (&wop, op2); ··· 1488 1488 return result; 1489 1489 } 1490 1490 1491 - unsigned64 1491 + uint64_t 1492 1492 convert_ps (sim_cpu *cpu, 1493 1493 address_word cia, 1494 1494 int rm, 1495 - unsigned64 op, 1495 + uint64_t op, 1496 1496 FP_formats from, 1497 1497 FP_formats to) 1498 1498 { 1499 1499 sim_fpu wop_u, wop_l; 1500 1500 sim_fpu_round round = rounding_mode (rm); 1501 1501 sim_fpu_denorm denorm = denorm_mode (cpu); 1502 - unsigned32 res_u, res_l; 1503 - unsigned64 result; 1502 + uint32_t res_u, res_l; 1503 + uint64_t result; 1504 1504 sim_fpu_status status_u = 0, status_l = 0; 1505 1505 1506 1506 /* As convert, but used only for paired values (formats PS, PW) */ ··· 1527 1527 case fmt_word: /* fmt_pw */ 1528 1528 status_u |= sim_fpu_to32u (&res_u, &wop_u, round); 1529 1529 status_l |= sim_fpu_to32u (&res_l, &wop_l, round); 1530 - result = (((unsigned64)res_u) << 32) | (unsigned64)res_l; 1530 + result = (((uint64_t)res_u) << 32) | (uint64_t)res_l; 1531 1531 break; 1532 1532 case fmt_ps: 1533 1533 status_u |= sim_fpu_round_32 (&wop_u, 0, round);
+324 -324
sim/mips/dsp.igen
··· 25 25 :function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat 26 26 { 27 27 int i; 28 - signed32 h0 = 0; 29 - signed16 h1, h2; 30 - unsigned32 v1 = GPR[rs]; 31 - unsigned32 v2 = GPR[rt]; 32 - unsigned32 result = 0; 28 + int32_t h0 = 0; 29 + int16_t h1, h2; 30 + uint32_t v1 = GPR[rs]; 31 + uint32_t v2 = GPR[rt]; 32 + uint32_t result = 0; 33 33 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 34 34 { 35 - h1 = (signed16)(v1 & 0xffff); 36 - h2 = (signed16)(v2 & 0xffff); 35 + h1 = (int16_t)(v1 & 0xffff); 36 + h2 = (int16_t)(v2 & 0xffff); 37 37 if (op == 0) // ADD 38 - h0 = (signed32)h1 + (signed32)h2; 38 + h0 = (int32_t)h1 + (int32_t)h2; 39 39 else if (op == 1) // SUB 40 - h0 = (signed32)h1 - (signed32)h2; 40 + h0 = (int32_t)h1 - (int32_t)h2; 41 41 else // MUL 42 - h0 = (signed32)h1 * (signed32)h2; 43 - if (h0 > (signed32)0x7fff || h0 < (signed32)0xffff8000) 42 + h0 = (int32_t)h1 * (int32_t)h2; 43 + if (h0 > (int32_t)0x7fff || h0 < (int32_t)0xffff8000) 44 44 { 45 45 if (op == 0 || op == 1) // ADD, SUB 46 46 DSPCR |= DSPCR_OUFLAG4; ··· 48 48 DSPCR |= DSPCR_OUFLAG5; 49 49 if (sat == 1) 50 50 { 51 - if (h0 > (signed32)0x7fff) 51 + if (h0 > (int32_t)0x7fff) 52 52 h0 = 0x7fff; 53 53 else 54 54 h0 = 0x8000; 55 55 } 56 56 } 57 - result |= ((unsigned32)((unsigned16)h0) << i); 57 + result |= ((uint32_t)((uint16_t)h0) << i); 58 58 } 59 59 GPR[rd] = EXTEND32 (result); 60 60 } ··· 62 62 // op: 0 = ADD, 1 = SUB 63 63 :function:::void:do_w_op:int rd, int rs, int rt, int op 64 64 { 65 - signed64 h0; 66 - signed32 h1, h2; 67 - unsigned32 v1 = GPR[rs]; 68 - unsigned32 v2 = GPR[rt]; 69 - unsigned32 result = 0; 70 - h1 = (signed32)v1; 71 - h2 = (signed32)v2; 65 + int64_t h0; 66 + int32_t h1, h2; 67 + uint32_t v1 = GPR[rs]; 68 + uint32_t v2 = GPR[rt]; 69 + uint32_t result = 0; 70 + h1 = (int32_t)v1; 71 + h2 = (int32_t)v2; 72 72 if (op == 0) // ADD 73 - h0 = (signed64)h1 + (signed64)h2; 73 + h0 = (int64_t)h1 + (int64_t)h2; 74 74 else // SUB 75 - h0 = (signed64)h1 - (signed64)h2; 75 + h0 = (int64_t)h1 - (int64_t)h2; 76 76 if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) 77 77 { 78 78 DSPCR |= DSPCR_OUFLAG4; ··· 89 89 :function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat 90 90 { 91 91 int i; 92 - unsigned32 h0; 93 - unsigned8 h1, h2; 94 - unsigned32 v1 = GPR[rs]; 95 - unsigned32 v2 = GPR[rt]; 96 - unsigned32 result = 0; 92 + uint32_t h0; 93 + uint8_t h1, h2; 94 + uint32_t v1 = GPR[rs]; 95 + uint32_t v2 = GPR[rt]; 96 + uint32_t result = 0; 97 97 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) 98 98 { 99 - h1 = (unsigned8)(v1 & 0xff); 100 - h2 = (unsigned8)(v2 & 0xff); 99 + h1 = (uint8_t)(v1 & 0xff); 100 + h2 = (uint8_t)(v2 & 0xff); 101 101 if (op == 0) // ADD 102 - h0 = (unsigned32)h1 + (unsigned32)h2; 102 + h0 = (uint32_t)h1 + (uint32_t)h2; 103 103 else // SUB 104 - h0 = (unsigned32)h1 - (unsigned32)h2; 104 + h0 = (uint32_t)h1 - (uint32_t)h2; 105 105 if (h0 & 0x100) 106 106 { 107 107 DSPCR |= DSPCR_OUFLAG4; ··· 113 113 h0 = 0; 114 114 } 115 115 } 116 - result |= ((unsigned32)((unsigned8)h0) << i); 116 + result |= ((uint32_t)((uint8_t)h0) << i); 117 117 } 118 118 GPR[rd] = EXTEND32 (result); 119 119 } ··· 122 122 :function:::void:do_qb_shift:int rd, int rt, int shift, int op 123 123 { 124 124 int i, j; 125 - unsigned8 h0; 126 - unsigned32 v1 = GPR[rt]; 127 - unsigned32 result = 0; 125 + uint8_t h0; 126 + uint32_t v1 = GPR[rt]; 127 + uint32_t result = 0; 128 128 for (i = 0; i < 32; i += 8, v1 >>= 8) 129 129 { 130 - h0 = (unsigned8)(v1 & 0xff); 130 + h0 = (uint8_t)(v1 & 0xff); 131 131 if (op == 0) // left 132 132 { 133 133 for (j = 7; j >= 8 - shift; j--) ··· 142 142 } 143 143 else // right 144 144 h0 = h0 >> shift; 145 - result |= ((unsigned32)h0 << i); 145 + result |= ((uint32_t)h0 << i); 146 146 } 147 147 GPR[rd] = EXTEND32 (result); 148 148 } ··· 152 152 :function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat 153 153 { 154 154 int i, j; 155 - signed16 h0; 156 - unsigned32 v1 = GPR[rt]; 157 - unsigned32 result = 0; 155 + int16_t h0; 156 + uint32_t v1 = GPR[rt]; 157 + uint32_t result = 0; 158 158 int setcond; 159 159 for (i = 0; i < 32; i += 16, v1 >>= 16) 160 160 { 161 - h0 = (signed16)(v1 & 0xffff); 161 + h0 = (int16_t)(v1 & 0xffff); 162 162 if (op == 0) // left 163 163 { 164 164 setcond = 0; ··· 203 203 h0 = h0 >> shift; 204 204 } 205 205 206 - result |= ((unsigned32)((unsigned16)h0) << i); 206 + result |= ((uint32_t)((uint16_t)h0) << i); 207 207 } 208 208 GPR[rd] = EXTEND32 (result); 209 209 } ··· 211 211 :function:::void:do_w_shll:int rd, int rt, int shift 212 212 { 213 213 int i; 214 - unsigned32 v1 = GPR[rt]; 215 - unsigned32 result = 0; 214 + uint32_t v1 = GPR[rt]; 215 + uint32_t result = 0; 216 216 int setcond = 0; 217 217 if (v1 & (1 << 31)) 218 218 { ··· 250 250 :function:::void:do_ph_s_absq:int rd, int rt 251 251 { 252 252 int i; 253 - signed16 h0; 254 - unsigned32 v1 = GPR[rt]; 255 - unsigned32 result = 0; 253 + int16_t h0; 254 + uint32_t v1 = GPR[rt]; 255 + uint32_t result = 0; 256 256 for (i = 0; i < 32; i += 16, v1 >>= 16) 257 257 { 258 - h0 = (signed16)(v1 & 0xffff); 259 - if (h0 == (signed16)0x8000) 258 + h0 = (int16_t)(v1 & 0xffff); 259 + if (h0 == (int16_t)0x8000) 260 260 { 261 261 DSPCR |= DSPCR_OUFLAG4; 262 262 h0 = 0x7fff; 263 263 } 264 264 else if (h0 & 0x8000) 265 265 h0 = -h0; 266 - result |= ((unsigned32)((unsigned16)h0) << i); 266 + result |= ((uint32_t)((uint16_t)h0) << i); 267 267 } 268 268 GPR[rd] = EXTEND32 (result); 269 269 } 270 270 271 271 :function:::void:do_w_s_absq:int rd, int rt 272 272 { 273 - unsigned32 v1 = GPR[rt]; 274 - signed32 h0 = (signed32)v1; 275 - if (h0 == (signed32)0x80000000) 273 + uint32_t v1 = GPR[rt]; 274 + int32_t h0 = (int32_t)v1; 275 + if (h0 == (int32_t)0x80000000) 276 276 { 277 277 DSPCR |= DSPCR_OUFLAG4; 278 278 h0 = 0x7fffffff; ··· 285 285 :function:::void:do_qb_s_absq:int rd, int rt 286 286 { 287 287 int i; 288 - signed8 q0; 289 - unsigned32 v1 = GPR[rt]; 290 - unsigned32 result = 0; 288 + int8_t q0; 289 + uint32_t v1 = GPR[rt]; 290 + uint32_t result = 0; 291 291 for (i = 0; i < 32; i += 8, v1 >>= 8) 292 292 { 293 - q0 = (signed8)(v1 & 0xff); 294 - if (q0 == (signed8)0x80) 293 + q0 = (int8_t)(v1 & 0xff); 294 + if (q0 == (int8_t)0x80) 295 295 { 296 296 DSPCR |= DSPCR_OUFLAG4; 297 297 q0 = 0x7f; 298 298 } 299 299 else if (q0 & 0x80) 300 300 q0 = -q0; 301 - result |= ((unsigned32)((unsigned8)q0) << i); 301 + result |= ((uint32_t)((uint8_t)q0) << i); 302 302 } 303 303 GPR[rd] = EXTEND32 (result); 304 304 } 305 305 306 306 :function:::void:do_addsc:int rd, int rs, int rt 307 307 { 308 - unsigned32 v1 = GPR[rs]; 309 - unsigned32 v2 = GPR[rt]; 310 - unsigned64 h0; 311 - h0 = (unsigned64)v1 + (unsigned64)v2; 308 + uint32_t v1 = GPR[rs]; 309 + uint32_t v2 = GPR[rt]; 310 + uint64_t h0; 311 + h0 = (uint64_t)v1 + (uint64_t)v2; 312 312 if (h0 & 0x100000000LL) 313 313 DSPCR |= DSPCR_CARRY; 314 314 GPR[rd] = EXTEND32 (h0); ··· 316 316 317 317 :function:::void:do_addwc:int rd, int rs, int rt 318 318 { 319 - unsigned32 v1 = GPR[rs]; 320 - unsigned32 v2 = GPR[rt]; 321 - unsigned64 h0; 322 - signed32 h1 = (signed32) v1; 323 - signed32 h2 = (signed32) v2; 324 - h0 = (signed64)h1 + (signed64)h2 325 - + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK); 319 + uint32_t v1 = GPR[rs]; 320 + uint32_t v2 = GPR[rt]; 321 + uint64_t h0; 322 + int32_t h1 = (int32_t) v1; 323 + int32_t h2 = (int32_t) v2; 324 + h0 = (int64_t)h1 + (int64_t)h2 325 + + (int64_t)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK); 326 326 if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000)) 327 327 DSPCR |= DSPCR_OUFLAG4; 328 328 GPR[rd] = EXTEND32 (h0); ··· 331 331 :function:::void:do_bitrev:int rd, int rt 332 332 { 333 333 int i; 334 - unsigned32 v1 = GPR[rt]; 335 - unsigned32 h1 = 0; 334 + uint32_t v1 = GPR[rt]; 335 + uint32_t h1 = 0; 336 336 for (i = 0; i < 16; i++) 337 337 { 338 338 if (v1 & (1 << i)) ··· 344 344 // op: 0 = EXTPV, 1 = EXTPDPV 345 345 :function:::void:do_extpv:int rt, int ac, int rs, int op 346 346 { 347 - unsigned32 size = GPR[rs] & 0x1f; 347 + uint32_t size = GPR[rs] & 0x1f; 348 348 do_extp (SD_, rt, ac, size, op); 349 349 } 350 350 351 351 // op: 0 = EXTRV, 1 = EXTRV_R, 2 = EXTRV_RS 352 352 :function:::void:do_extrv:int rt, int ac, int rs, int op 353 353 { 354 - unsigned32 shift = GPR[rs] & 0x1f; 354 + uint32_t shift = GPR[rs] & 0x1f; 355 355 do_w_extr (SD_, rt, ac, shift, op); 356 356 } 357 357 358 358 :function:::void:do_extrv_s_h:int rt, int ac, int rs 359 359 { 360 - unsigned32 shift = GPR[rs] & 0x1f; 360 + uint32_t shift = GPR[rs] & 0x1f; 361 361 do_h_extr (SD_, rt, ac, shift); 362 362 } 363 363 364 364 :function:::void:do_insv:int rt, int rs 365 365 { 366 - unsigned32 v1 = GPR[rs]; 367 - unsigned32 v2 = GPR[rt]; 368 - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 369 - unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK; 370 - unsigned32 mask1, mask2, mask3, result; 366 + uint32_t v1 = GPR[rs]; 367 + uint32_t v2 = GPR[rt]; 368 + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 369 + uint32_t size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK; 370 + uint32_t mask1, mask2, mask3, result; 371 371 if (size < 32) 372 372 mask1 = (1 << size) - 1; 373 373 else ··· 394 394 395 395 :function:::void:do_modsub:int rd, int rs, int rt 396 396 { 397 - unsigned32 result = 0; 398 - unsigned32 v1 = GPR[rs]; 399 - unsigned32 v2 = GPR[rt]; 400 - unsigned32 decr = v2 & 0xff; 401 - unsigned32 lastindex = (v2 & 0xffff00) >> 8; 397 + uint32_t result = 0; 398 + uint32_t v1 = GPR[rs]; 399 + uint32_t v2 = GPR[rt]; 400 + uint32_t decr = v2 & 0xff; 401 + uint32_t lastindex = (v2 & 0xffff00) >> 8; 402 402 if (v1 == 0) 403 403 result = lastindex; 404 404 else ··· 408 408 409 409 :function:::void:do_mthlip:int rs, int ac 410 410 { 411 - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 411 + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 412 412 DSPHI(ac) = DSPLO(ac); 413 413 DSPLO(ac) = GPR[rs]; 414 414 if (pos >= 32) ··· 422 422 :function:::void:do_mulsaq_s_w_ph:int ac, int rs, int rt 423 423 { 424 424 int i; 425 - unsigned32 v1 = GPR[rs]; 426 - unsigned32 v2 = GPR[rt]; 427 - signed16 h1, h2; 428 - signed32 result; 429 - unsigned32 lo = DSPLO(ac); 430 - unsigned32 hi = DSPHI(ac); 431 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 425 + uint32_t v1 = GPR[rs]; 426 + uint32_t v2 = GPR[rt]; 427 + int16_t h1, h2; 428 + int32_t result; 429 + uint32_t lo = DSPLO(ac); 430 + uint32_t hi = DSPHI(ac); 431 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 432 432 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 433 433 { 434 - h1 = (signed16)(v1 & 0xffff); 435 - h2 = (signed16)(v2 & 0xffff); 436 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 434 + h1 = (int16_t)(v1 & 0xffff); 435 + h2 = (int16_t)(v2 & 0xffff); 436 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 437 437 { 438 438 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 439 - result = (signed32) 0x7fffffff; 439 + result = (int32_t) 0x7fffffff; 440 440 } 441 441 else 442 - result = ((signed32)h1 * (signed32)h2) << 1; 442 + result = ((int32_t)h1 * (int32_t)h2) << 1; 443 443 444 444 if (i == 0) 445 - prod -= (signed64) result; 445 + prod -= (int64_t) result; 446 446 else 447 - prod += (signed64) result; 447 + prod += (int64_t) result; 448 448 } 449 449 DSPLO(ac) = EXTEND32 (prod); 450 450 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 453 453 :function:::void:do_ph_packrl:int rd, int rs, int rt 454 454 { 455 455 456 - unsigned32 v1 = GPR[rs]; 457 - unsigned32 v2 = GPR[rt]; 456 + uint32_t v1 = GPR[rs]; 457 + uint32_t v2 = GPR[rt]; 458 458 GPR[rd] = EXTEND32 ((v1 << 16) + (v2 >> 16)); 459 459 } 460 460 461 461 :function:::void:do_qb_pick:int rd, int rs, int rt 462 462 { 463 463 int i, j; 464 - unsigned32 v1 = GPR[rs]; 465 - unsigned32 v2 = GPR[rt]; 466 - unsigned8 h1, h2; 467 - unsigned32 result = 0; 464 + uint32_t v1 = GPR[rs]; 465 + uint32_t v2 = GPR[rt]; 466 + uint8_t h1, h2; 467 + uint32_t result = 0; 468 468 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 469 469 { 470 - h1 = (unsigned8)(v1 & 0xff); 471 - h2 = (unsigned8)(v2 & 0xff); 470 + h1 = (uint8_t)(v1 & 0xff); 471 + h2 = (uint8_t)(v2 & 0xff); 472 472 if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) 473 - result |= (unsigned32)(h1 << i); 473 + result |= (uint32_t)(h1 << i); 474 474 else 475 - result |= (unsigned32)(h2 << i); 475 + result |= (uint32_t)(h2 << i); 476 476 } 477 477 GPR[rd] = EXTEND32 (result); 478 478 } ··· 480 480 :function:::void:do_ph_pick:int rd, int rs, int rt 481 481 { 482 482 int i, j; 483 - unsigned32 v1 = GPR[rs]; 484 - unsigned32 v2 = GPR[rt]; 485 - unsigned16 h1, h2; 486 - unsigned32 result = 0; 483 + uint32_t v1 = GPR[rs]; 484 + uint32_t v2 = GPR[rt]; 485 + uint16_t h1, h2; 486 + uint32_t result = 0; 487 487 for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) 488 488 { 489 - h1 = (unsigned16)(v1 & 0xffff); 490 - h2 = (unsigned16)(v2 & 0xffff); 489 + h1 = (uint16_t)(v1 & 0xffff); 490 + h2 = (uint16_t)(v2 & 0xffff); 491 491 if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j))) 492 - result |= (unsigned32)(h1 << i); 492 + result |= (uint32_t)(h1 << i); 493 493 else 494 - result |= (unsigned32)(h2 << i); 494 + result |= (uint32_t)(h2 << i); 495 495 } 496 496 GPR[rd] = EXTEND32 (result); 497 497 } ··· 499 499 // op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA 500 500 :function:::void:do_qb_ph_precequ:int rd, int rt, int op 501 501 { 502 - unsigned32 v1 = GPR[rt]; 502 + uint32_t v1 = GPR[rt]; 503 503 if (op == 0) 504 504 GPR[rd] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7); 505 505 else if (op == 1) ··· 513 513 // op: 0 = QBR, 1 = QBRA, 2 = QBL, 3 = QBLA 514 514 :function:::void:do_qb_ph_preceu:int rd, int rt, int op 515 515 { 516 - unsigned32 v1 = GPR[rt]; 516 + uint32_t v1 = GPR[rt]; 517 517 if (op == 0) 518 518 GPR[rd] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff); 519 519 else if (op == 1) ··· 527 527 // op: 0 = .PHL, 1 = PHR 528 528 :function:::void:do_w_preceq:int rd, int rt, int op 529 529 { 530 - unsigned32 v1 = GPR[rt]; 530 + uint32_t v1 = GPR[rt]; 531 531 if (op == 0) 532 532 GPR[rd] = EXTEND32 (v1 & 0xffff0000); 533 533 else if (op == 1) ··· 536 536 537 537 :function:::void:do_w_ph_precrq:int rd, int rs, int rt 538 538 { 539 - unsigned32 v1 = GPR[rs]; 540 - unsigned32 v2 = GPR[rt]; 541 - unsigned32 tempu = (v1 & 0xffff0000) >> 16; 542 - unsigned32 tempv = (v2 & 0xffff0000) >> 16; 539 + uint32_t v1 = GPR[rs]; 540 + uint32_t v2 = GPR[rt]; 541 + uint32_t tempu = (v1 & 0xffff0000) >> 16; 542 + uint32_t tempv = (v2 & 0xffff0000) >> 16; 543 543 GPR[rd] = EXTEND32 ((tempu << 16) | tempv); 544 544 } 545 545 546 546 // sat: 0 = PRECRQ.QB.PH, 1 = PRECRQU_S.QB.PH 547 547 :function:::void:do_ph_qb_precrq:int rd, int rs, int rt, int sat 548 548 { 549 - unsigned32 v1 = GPR[rs]; 550 - unsigned32 v2 = GPR[rt]; 551 - unsigned32 tempu = 0, tempv = 0, tempw = 0, tempx = 0; 549 + uint32_t v1 = GPR[rs]; 550 + uint32_t v2 = GPR[rt]; 551 + uint32_t tempu = 0, tempv = 0, tempw = 0, tempx = 0; 552 552 if (sat == 0) 553 553 { 554 554 tempu = (v1 & 0xff000000) >> 24; ··· 563 563 DSPCR |= DSPCR_OUFLAG6; 564 564 tempu = 0; 565 565 } 566 - else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80)) 566 + else if (!(v1 & 0x80000000) && ((v1 >> 16) > (uint32_t)0x7f80)) 567 567 { 568 568 DSPCR |= DSPCR_OUFLAG6; 569 569 tempu = 0xff; ··· 575 575 DSPCR |= DSPCR_OUFLAG6; 576 576 tempv = 0; 577 577 } 578 - else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80)) 578 + else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (uint32_t)0x7f80)) 579 579 { 580 580 DSPCR |= DSPCR_OUFLAG6; 581 581 tempv = 0xff; ··· 587 587 DSPCR |= DSPCR_OUFLAG6; 588 588 tempw = 0; 589 589 } 590 - else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80)) 590 + else if (!(v2 & 0x80000000) && ((v2 >> 16) > (uint32_t)0x7f80)) 591 591 { 592 592 DSPCR |= DSPCR_OUFLAG6; 593 593 tempw = 0xff; ··· 599 599 DSPCR |= DSPCR_OUFLAG6; 600 600 tempx = 0; 601 601 } 602 - else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80)) 602 + else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (uint32_t)0x7f80)) 603 603 { 604 604 DSPCR |= DSPCR_OUFLAG6; 605 605 tempx = 0xff; ··· 612 612 613 613 :function:::void:do_w_ph_rs_precrq:int rd, int rs, int rt 614 614 { 615 - unsigned32 v1 = GPR[rs]; 616 - unsigned32 v2 = GPR[rt]; 617 - signed32 h1 = (signed32)v1; 618 - signed32 h2 = (signed32)v2; 619 - signed64 temp1 = (signed64)h1 + (signed64)0x8000; 620 - signed32 temp2; 621 - signed64 temp3 = (signed64)h2 + (signed64)0x8000; 622 - signed32 temp4; 615 + uint32_t v1 = GPR[rs]; 616 + uint32_t v2 = GPR[rt]; 617 + int32_t h1 = (int32_t)v1; 618 + int32_t h2 = (int32_t)v2; 619 + int64_t temp1 = (int64_t)h1 + (int64_t)0x8000; 620 + int32_t temp2; 621 + int64_t temp3 = (int64_t)h2 + (int64_t)0x8000; 622 + int32_t temp4; 623 623 if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000)) 624 624 { 625 625 DSPCR |= DSPCR_OUFLAG6; 626 626 temp2 = 0x7fff; 627 627 } 628 628 else 629 - temp2 = (signed32)((temp1 & 0xffff0000) >> 16); 629 + temp2 = (int32_t)((temp1 & 0xffff0000) >> 16); 630 630 if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000)) 631 631 { 632 632 DSPCR |= DSPCR_OUFLAG6; 633 633 temp4 = 0x7fff; 634 634 } 635 635 else 636 - temp4 = (signed32)((temp3 & 0xffff0000) >> 16); 636 + temp4 = (int32_t)((temp3 & 0xffff0000) >> 16); 637 637 GPR[rd] = EXTEND32 ((temp2 << 16) | temp4); 638 638 } 639 639 640 640 :function:::void:do_qb_w_raddu:int rd, int rs 641 641 { 642 642 int i; 643 - unsigned8 h0; 644 - unsigned32 v1 = GPR[rs]; 645 - unsigned32 result = 0; 643 + uint8_t h0; 644 + uint32_t v1 = GPR[rs]; 645 + uint32_t result = 0; 646 646 for (i = 0; i < 32; i += 8, v1 >>= 8) 647 647 { 648 - h0 = (unsigned8)(v1 & 0xff); 649 - result += (unsigned32)h0; 648 + h0 = (uint8_t)(v1 & 0xff); 649 + result += (uint32_t)h0; 650 650 } 651 651 GPR[rd] = EXTEND32 (result); 652 652 } 653 653 654 654 :function:::void:do_rddsp:int rd, int mask 655 655 { 656 - unsigned32 result = 0; 656 + uint32_t result = 0; 657 657 if (mask & 0x1) 658 658 { 659 659 result &= (~DSPCR_POS_SMASK); ··· 694 694 GPR[rd] = EXTEND32 ((p2 << 24) | (p2 << 16) | (p2 << 8) | p2); 695 695 else if (op == 1) 696 696 { 697 - unsigned32 v1 = GPR[p2] & 0xff; 697 + uint32_t v1 = GPR[p2] & 0xff; 698 698 GPR[rd] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1); 699 699 } 700 700 else if (op == 2) 701 701 { 702 - signed32 v1 = p2; 702 + int32_t v1 = p2; 703 703 if (v1 & 0x200) 704 704 v1 |= 0xfffffc00; 705 705 GPR[rd] = EXTEND32 ((v1 << 16) | (v1 & 0xffff)); 706 706 } 707 707 else if (op == 3) 708 708 { 709 - unsigned32 v1 = GPR[p2]; 709 + uint32_t v1 = GPR[p2]; 710 710 v1 = v1 & 0xffff; 711 711 GPR[rd] = EXTEND32 ((v1 << 16) | v1); 712 712 } ··· 714 714 715 715 :function:::void:do_shilov:int ac, int rs 716 716 { 717 - signed32 shift = GPR[rs] & 0x3f; 717 + int32_t shift = GPR[rs] & 0x3f; 718 718 do_shilo (SD_, ac, shift); 719 719 } 720 720 ··· 722 722 // sat: 0 = normal, 1 = saturate/rounding 723 723 :function:::void:do_ph_shl:int rd, int rt, int rs, int op, int sat 724 724 { 725 - unsigned32 shift = GPR[rs] & 0xf; 725 + uint32_t shift = GPR[rs] & 0xf; 726 726 do_ph_shift (SD_, rd, rt, shift, op, sat); 727 727 } 728 728 729 729 // op: 0 = SHLLV, 1 = SHRLV 730 730 :function:::void:do_qb_shl:int rd, int rt, int rs, int op 731 731 { 732 - unsigned32 shift = GPR[rs] & 0x7; 732 + uint32_t shift = GPR[rs] & 0x7; 733 733 do_qb_shift (SD_, rd, rt, shift, op); 734 734 } 735 735 736 736 :function:::void:do_w_s_shllv:int rd, int rt, int rs 737 737 { 738 - unsigned32 shift = GPR[rs] & 0x1f; 738 + uint32_t shift = GPR[rs] & 0x1f; 739 739 do_w_shll (SD_, rd, rt, shift); 740 740 } 741 741 742 742 :function:::void:do_ph_shrlv:int rd, int rt, int rs 743 743 { 744 - unsigned32 shift = GPR[rs] & 0xf; 744 + uint32_t shift = GPR[rs] & 0xf; 745 745 do_ph_shrl (SD_, rd, rt, shift); 746 746 } 747 747 748 748 :function:::void:do_w_r_shrav:int rd, int rt, int rs 749 749 { 750 - unsigned32 shift = GPR[rs] & 0x1f; 750 + uint32_t shift = GPR[rs] & 0x1f; 751 751 do_w_shra (SD_, rd, rt, shift); 752 752 } 753 753 754 754 :function:::void:do_wrdsp:int rs, int mask 755 755 { 756 - unsigned32 v1 = GPR[rs]; 756 + uint32_t v1 = GPR[rs]; 757 757 if (mask & 0x1) 758 758 { 759 759 DSPCR &= (~DSPCR_POS_SMASK); ··· 789 789 // round: 0 = no rounding, 1 = rounding 790 790 :function:::void:do_qb_shrav:int rd, int rt, int rs, int round 791 791 { 792 - unsigned32 shift = GPR[rs] & 0x7; 792 + uint32_t shift = GPR[rs] & 0x7; 793 793 do_qb_shra (SD_, rd, rt, shift, round); 794 794 } 795 795 796 796 :function:::void:do_append:int rt, int rs, int sa 797 797 { 798 - unsigned32 v0 = GPR[rs]; 799 - unsigned32 v1 = GPR[rt]; 800 - unsigned32 result; 801 - unsigned32 mask = (1 << sa) - 1; 798 + uint32_t v0 = GPR[rs]; 799 + uint32_t v1 = GPR[rt]; 800 + uint32_t result; 801 + uint32_t mask = (1 << sa) - 1; 802 802 result = (v1 << sa) | (v0 & mask); 803 803 GPR[rt] = EXTEND32 (result); 804 804 } 805 805 806 806 :function:::void:do_balign:int rt, int rs, int bp 807 807 { 808 - unsigned32 v0 = GPR[rs]; 809 - unsigned32 v1 = GPR[rt]; 810 - unsigned32 result; 808 + uint32_t v0 = GPR[rs]; 809 + uint32_t v1 = GPR[rt]; 810 + uint32_t result; 811 811 if (bp == 0) 812 812 result = v1; 813 813 else ··· 818 818 :function:::void:do_ph_w_mulsa:int ac, int rs, int rt 819 819 { 820 820 int i; 821 - unsigned32 v1 = GPR[rs]; 822 - unsigned32 v2 = GPR[rt]; 823 - signed16 h1, h2; 824 - signed32 result; 825 - unsigned32 lo = DSPLO(ac); 826 - unsigned32 hi = DSPHI(ac); 827 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 821 + uint32_t v1 = GPR[rs]; 822 + uint32_t v2 = GPR[rt]; 823 + int16_t h1, h2; 824 + int32_t result; 825 + uint32_t lo = DSPLO(ac); 826 + uint32_t hi = DSPHI(ac); 827 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 828 828 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 829 829 { 830 - h1 = (signed16)(v1 & 0xffff); 831 - h2 = (signed16)(v2 & 0xffff); 832 - result = (signed32)h1 * (signed32)h2; 830 + h1 = (int16_t)(v1 & 0xffff); 831 + h2 = (int16_t)(v2 & 0xffff); 832 + result = (int32_t)h1 * (int32_t)h2; 833 833 834 834 if (i == 0) 835 - prod -= (signed64) result; 835 + prod -= (int64_t) result; 836 836 else 837 - prod += (signed64) result; 837 + prod += (int64_t) result; 838 838 } 839 839 DSPLO(ac) = EXTEND32 (prod); 840 840 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 842 842 843 843 :function:::void:do_ph_qb_precr:int rd, int rs, int rt 844 844 { 845 - unsigned32 v1 = GPR[rs]; 846 - unsigned32 v2 = GPR[rt]; 847 - unsigned32 tempu = (v1 & 0xff0000) >> 16; 848 - unsigned32 tempv = (v1 & 0xff); 849 - unsigned32 tempw = (v2 & 0xff0000) >> 16; 850 - unsigned32 tempx = (v2 & 0xff); 845 + uint32_t v1 = GPR[rs]; 846 + uint32_t v2 = GPR[rt]; 847 + uint32_t tempu = (v1 & 0xff0000) >> 16; 848 + uint32_t tempv = (v1 & 0xff); 849 + uint32_t tempw = (v2 & 0xff0000) >> 16; 850 + uint32_t tempx = (v2 & 0xff); 851 851 GPR[rd] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx); 852 852 } 853 853 854 854 :function:::void:do_prepend:int rt, int rs, int sa 855 855 { 856 - unsigned32 v0 = GPR[rs]; 857 - unsigned32 v1 = GPR[rt]; 858 - unsigned32 result; 856 + uint32_t v0 = GPR[rs]; 857 + uint32_t v1 = GPR[rt]; 858 + uint32_t result; 859 859 if (sa == 0) 860 860 result = v1; 861 861 else ··· 865 865 866 866 :function:::void:do_w_shra:int rd, int rt, int shift 867 867 { 868 - unsigned32 result = GPR[rt]; 869 - signed32 h0 = (signed32)result; 868 + uint32_t result = GPR[rt]; 869 + int32_t h0 = (int32_t)result; 870 870 if (shift != 0 && (h0 & (1 << (shift-1)))) 871 871 h0 = (h0 >> shift) + 1; 872 872 else ··· 1200 1200 :function:::void:do_qb_muleu:int rd, int rs, int rt, int loc 1201 1201 { 1202 1202 int i; 1203 - unsigned32 result = 0; 1204 - unsigned32 v1 = GPR[rs]; 1205 - unsigned32 v2 = GPR[rt]; 1206 - unsigned16 h1, h2; 1207 - unsigned32 prod; 1203 + uint32_t result = 0; 1204 + uint32_t v1 = GPR[rs]; 1205 + uint32_t v2 = GPR[rt]; 1206 + uint16_t h1, h2; 1207 + uint32_t prod; 1208 1208 if (loc == 0) 1209 1209 v1 >>= 16; 1210 1210 for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16) 1211 1211 { 1212 - h1 = (unsigned16)(v1 & 0xff); 1213 - h2 = (unsigned16)(v2 & 0xffff); 1214 - prod = (unsigned32)h1 * (unsigned32)h2; 1212 + h1 = (uint16_t)(v1 & 0xff); 1213 + h2 = (uint16_t)(v2 & 0xffff); 1214 + prod = (uint32_t)h1 * (uint32_t)h2; 1215 1215 if (prod > 0xffff) 1216 1216 { 1217 1217 DSPCR |= DSPCR_OUFLAG5; 1218 1218 prod = 0xffff; 1219 1219 } 1220 - result |= ((unsigned32)prod << i); 1220 + result |= ((uint32_t)prod << i); 1221 1221 } 1222 1222 GPR[rd] = EXTEND32 (result); 1223 1223 } ··· 1240 1240 :function:::void:do_ph_mulq:int rd, int rs, int rt, int round 1241 1241 { 1242 1242 int i; 1243 - unsigned32 result = 0; 1244 - unsigned32 v1 = GPR[rs]; 1245 - unsigned32 v2 = GPR[rt]; 1246 - signed16 h1, h2; 1247 - signed32 prod; 1243 + uint32_t result = 0; 1244 + uint32_t v1 = GPR[rs]; 1245 + uint32_t v2 = GPR[rt]; 1246 + int16_t h1, h2; 1247 + int32_t prod; 1248 1248 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 1249 1249 { 1250 - h1 = (signed16)(v1 & 0xffff); 1251 - h2 = (signed16)(v2 & 0xffff); 1252 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 1250 + h1 = (int16_t)(v1 & 0xffff); 1251 + h2 = (int16_t)(v2 & 0xffff); 1252 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 1253 1253 { 1254 1254 DSPCR |= DSPCR_OUFLAG5; 1255 1255 prod = 0x7fffffff; 1256 1256 } 1257 1257 else 1258 1258 { 1259 - prod = ((signed32)h1 * (signed32)h2) << 1; 1259 + prod = ((int32_t)h1 * (int32_t)h2) << 1; 1260 1260 if (round == 1) 1261 - prod += (signed32)0x8000; 1261 + prod += (int32_t)0x8000; 1262 1262 } 1263 - result |= (((unsigned32)prod >> 16) << i); 1263 + result |= (((uint32_t)prod >> 16) << i); 1264 1264 } 1265 1265 GPR[rd] = EXTEND32 (result); 1266 1266 } ··· 1275 1275 // loc: 0 = phl, 1 = phr 1276 1276 :function:::void:do_ph_muleq:int rd, int rs, int rt, int loc 1277 1277 { 1278 - unsigned32 v1 = GPR[rs]; 1279 - unsigned32 v2 = GPR[rt]; 1280 - signed16 h1, h2; 1281 - signed32 prod; 1278 + uint32_t v1 = GPR[rs]; 1279 + uint32_t v2 = GPR[rt]; 1280 + int16_t h1, h2; 1281 + int32_t prod; 1282 1282 if (loc == 0) 1283 1283 { 1284 - h1 = (signed16)(v1 >> 16); 1285 - h2 = (signed16)(v2 >> 16); 1284 + h1 = (int16_t)(v1 >> 16); 1285 + h2 = (int16_t)(v2 >> 16); 1286 1286 } 1287 1287 else 1288 1288 { 1289 - h1 = (signed16)(v1 & 0xffff); 1290 - h2 = (signed16)(v2 & 0xffff); 1289 + h1 = (int16_t)(v1 & 0xffff); 1290 + h2 = (int16_t)(v2 & 0xffff); 1291 1291 } 1292 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 1292 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 1293 1293 { 1294 1294 DSPCR |= DSPCR_OUFLAG5; 1295 1295 prod = 0x7fffffff; 1296 1296 } 1297 1297 else 1298 - prod = ((signed32)h1 * (signed32)h2) << 1; 1298 + prod = ((int32_t)h1 * (int32_t)h2) << 1; 1299 1299 GPR[rd] = EXTEND32 (prod); 1300 1300 } 1301 1301 ··· 1318 1318 :function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc 1319 1319 { 1320 1320 int i; 1321 - unsigned32 v1 = GPR[rs]; 1322 - unsigned32 v2 = GPR[rt]; 1323 - unsigned8 h1, h2; 1324 - unsigned32 lo = DSPLO(ac); 1325 - unsigned32 hi = DSPHI(ac); 1326 - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; 1321 + uint32_t v1 = GPR[rs]; 1322 + uint32_t v2 = GPR[rt]; 1323 + uint8_t h1, h2; 1324 + uint32_t lo = DSPLO(ac); 1325 + uint32_t hi = DSPHI(ac); 1326 + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; 1327 1327 if (loc == 0) 1328 1328 { 1329 1329 v1 >>= 16; ··· 1331 1331 } 1332 1332 for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8) 1333 1333 { 1334 - h1 = (unsigned8)(v1 & 0xff); 1335 - h2 = (unsigned8)(v2 & 0xff); 1334 + h1 = (uint8_t)(v1 & 0xff); 1335 + h2 = (uint8_t)(v2 & 0xff); 1336 1336 if (op == 0) // DPAU 1337 - prod += (unsigned64)h1 * (unsigned64)h2; 1337 + prod += (uint64_t)h1 * (uint64_t)h2; 1338 1338 else // DPSU 1339 - prod -= (unsigned64)h1 * (unsigned64)h2; 1339 + prod -= (uint64_t)h1 * (uint64_t)h2; 1340 1340 } 1341 1341 DSPLO(ac) = EXTEND32 (prod); 1342 1342 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 1374 1374 :function:::void:do_ph_dot_product:int ac, int rs, int rt, int op 1375 1375 { 1376 1376 int i; 1377 - unsigned32 v1 = GPR[rs]; 1378 - unsigned32 v2 = GPR[rt]; 1379 - signed16 h1, h2; 1380 - signed32 result; 1381 - unsigned32 lo = DSPLO(ac); 1382 - unsigned32 hi = DSPHI(ac); 1383 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 1377 + uint32_t v1 = GPR[rs]; 1378 + uint32_t v2 = GPR[rt]; 1379 + int16_t h1, h2; 1380 + int32_t result; 1381 + uint32_t lo = DSPLO(ac); 1382 + uint32_t hi = DSPHI(ac); 1383 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 1384 1384 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 1385 1385 { 1386 - h1 = (signed16)(v1 & 0xffff); 1387 - h2 = (signed16)(v2 & 0xffff); 1388 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 1386 + h1 = (int16_t)(v1 & 0xffff); 1387 + h2 = (int16_t)(v2 & 0xffff); 1388 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 1389 1389 { 1390 1390 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 1391 - result = (signed32)0x7fffffff; 1391 + result = (int32_t)0x7fffffff; 1392 1392 } 1393 1393 else 1394 - result = ((signed32)h1 * (signed32)h2) << 1; 1394 + result = ((int32_t)h1 * (int32_t)h2) << 1; 1395 1395 1396 1396 if (op == 0) // DPAQ 1397 - prod += (signed64)result; 1397 + prod += (int64_t)result; 1398 1398 else // DPSQ 1399 - prod -= (signed64)result; 1399 + prod -= (int64_t)result; 1400 1400 } 1401 1401 DSPLO(ac) = EXTEND32 (prod); 1402 1402 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 1426 1426 // op: 0 = DPAQ 1 = DPSQ 1427 1427 :function:::void:do_w_dot_product:int ac, int rs, int rt, int op 1428 1428 { 1429 - unsigned32 v1 = GPR[rs]; 1430 - unsigned32 v2 = GPR[rt]; 1431 - signed32 h1, h2; 1432 - signed64 result; 1433 - unsigned32 lo = DSPLO(ac); 1434 - unsigned32 hi = DSPHI(ac); 1435 - unsigned32 resultlo; 1436 - unsigned32 resulthi; 1437 - unsigned32 carry; 1438 - unsigned64 temp1; 1439 - signed64 temp2; 1440 - h1 = (signed32) v1; 1441 - h2 = (signed32) v2; 1429 + uint32_t v1 = GPR[rs]; 1430 + uint32_t v2 = GPR[rt]; 1431 + int32_t h1, h2; 1432 + int64_t result; 1433 + uint32_t lo = DSPLO(ac); 1434 + uint32_t hi = DSPHI(ac); 1435 + uint32_t resultlo; 1436 + uint32_t resulthi; 1437 + uint32_t carry; 1438 + uint64_t temp1; 1439 + int64_t temp2; 1440 + h1 = (int32_t) v1; 1441 + h2 = (int32_t) v2; 1442 1442 if (h1 == 0x80000000 && h2 == 0x80000000) 1443 1443 { 1444 1444 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 1445 - result = (signed64) 0x7fffffffffffffffLL; 1445 + result = (int64_t) 0x7fffffffffffffffLL; 1446 1446 } 1447 1447 else 1448 - result = ((signed64)h1 * (signed64)h2) << 1; 1449 - resultlo = (unsigned32)(result); 1450 - resulthi = (unsigned32)(result >> 32); 1448 + result = ((int64_t)h1 * (int64_t)h2) << 1; 1449 + resultlo = (uint32_t)(result); 1450 + resulthi = (uint32_t)(result >> 32); 1451 1451 if (op ==0) // DPAQ 1452 1452 { 1453 - temp1 = (unsigned64)lo + (unsigned64)resultlo; 1454 - carry = (unsigned32)((temp1 >> 32) & 1); 1455 - temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) + 1456 - (signed64)((signed32)carry); 1453 + temp1 = (uint64_t)lo + (uint64_t)resultlo; 1454 + carry = (uint32_t)((temp1 >> 32) & 1); 1455 + temp2 = (int64_t)((int32_t)hi) + (int64_t)((int32_t)resulthi) + 1456 + (int64_t)((int32_t)carry); 1457 1457 } 1458 1458 else // DPSQ 1459 1459 { 1460 - temp1 = (unsigned64)lo - (unsigned64)resultlo; 1461 - carry = (unsigned32)((temp1 >> 32) & 1); 1462 - temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) - 1463 - (signed64)((signed32)carry); 1460 + temp1 = (uint64_t)lo - (uint64_t)resultlo; 1461 + carry = (uint32_t)((temp1 >> 32) & 1); 1462 + temp2 = (int64_t)((int32_t)hi) - (int64_t)((int32_t)resulthi) - 1463 + (int64_t)((int32_t)carry); 1464 1464 } 1465 1465 if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL)) 1466 1466 { ··· 1502 1502 :function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc 1503 1503 { 1504 1504 int i; 1505 - unsigned32 v1 = GPR[rs]; 1506 - unsigned32 v2 = GPR[rt]; 1507 - signed16 h1, h2; 1508 - signed32 result; 1509 - unsigned32 lo = DSPLO(ac); 1510 - unsigned32 hi = DSPHI(ac); 1511 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 1505 + uint32_t v1 = GPR[rs]; 1506 + uint32_t v2 = GPR[rt]; 1507 + int16_t h1, h2; 1508 + int32_t result; 1509 + uint32_t lo = DSPLO(ac); 1510 + uint32_t hi = DSPHI(ac); 1511 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 1512 1512 if (loc == 0) 1513 1513 { 1514 - h1 = (signed16)(v1 >> 16); 1515 - h2 = (signed16)(v2 >> 16); 1514 + h1 = (int16_t)(v1 >> 16); 1515 + h2 = (int16_t)(v2 >> 16); 1516 1516 } 1517 1517 else 1518 1518 { 1519 - h1 = (signed16)(v1 & 0xffff); 1520 - h2 = (signed16)(v2 & 0xffff); 1519 + h1 = (int16_t)(v1 & 0xffff); 1520 + h2 = (int16_t)(v2 & 0xffff); 1521 1521 } 1522 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 1522 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 1523 1523 { 1524 1524 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 1525 - result = (signed32)0x7fffffff; 1525 + result = (int32_t)0x7fffffff; 1526 1526 } 1527 1527 else 1528 - result = ((signed32)h1 * (signed32)h2) << 1; 1529 - prod += (signed64)result; 1528 + result = ((int32_t)h1 * (int32_t)h2) << 1; 1529 + prod += (int64_t)result; 1530 1530 if (op == 1) // MAQ_SA 1531 1531 { 1532 1532 if (prod & 0x8000000000000000LL) 1533 1533 { 1534 1534 for (i = 62; i >= 31; i--) 1535 1535 { 1536 - if (!(prod & ((signed64)1 << i))) 1536 + if (!(prod & ((int64_t)1 << i))) 1537 1537 { 1538 1538 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 1539 1539 prod = 0xffffffff80000000LL; ··· 1545 1545 { 1546 1546 for (i = 62; i >= 31; i--) 1547 1547 { 1548 - if (prod & ((signed64)1 << i)) 1548 + if (prod & ((int64_t)1 << i)) 1549 1549 { 1550 1550 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 1551 1551 prod = 0x7fffffff; ··· 1632 1632 :function:::void:do_qb_cmpu:int rs, int rt, int op 1633 1633 { 1634 1634 int i, j; 1635 - unsigned32 v1 = GPR[rs]; 1636 - unsigned32 v2 = GPR[rt]; 1637 - unsigned8 h1, h2; 1638 - unsigned32 mask; 1635 + uint32_t v1 = GPR[rs]; 1636 + uint32_t v2 = GPR[rt]; 1637 + uint8_t h1, h2; 1638 + uint32_t mask; 1639 1639 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 1640 1640 { 1641 - h1 = (unsigned8)(v1 & 0xff); 1642 - h2 = (unsigned8)(v2 & 0xff); 1641 + h1 = (uint8_t)(v1 & 0xff); 1642 + h2 = (uint8_t)(v2 & 0xff); 1643 1643 mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); 1644 1644 DSPCR &= mask; 1645 1645 if (op == 0) // EQ ··· 1676 1676 :function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op 1677 1677 { 1678 1678 int i, j; 1679 - unsigned32 v1 = GPR[rs]; 1680 - unsigned32 v2 = GPR[rt]; 1681 - unsigned8 h1, h2; 1682 - unsigned32 result = 0; 1679 + uint32_t v1 = GPR[rs]; 1680 + uint32_t v2 = GPR[rt]; 1681 + uint8_t h1, h2; 1682 + uint32_t result = 0; 1683 1683 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 1684 1684 { 1685 - h1 = (unsigned8)(v1 & 0xff); 1686 - h2 = (unsigned8)(v2 & 0xff); 1685 + h1 = (uint8_t)(v1 & 0xff); 1686 + h2 = (uint8_t)(v2 & 0xff); 1687 1687 if (op == 0) // EQ 1688 1688 result |= ((h1 == h2) << j); 1689 1689 else if (op == 1) // LT ··· 1719 1719 :function:::void:do_ph_cmpu:int rs, int rt, int op 1720 1720 { 1721 1721 int i, j; 1722 - unsigned32 v1 = GPR[rs]; 1723 - unsigned32 v2 = GPR[rt]; 1724 - signed16 h1, h2; 1725 - unsigned32 mask; 1722 + uint32_t v1 = GPR[rs]; 1723 + uint32_t v2 = GPR[rt]; 1724 + int16_t h1, h2; 1725 + uint32_t mask; 1726 1726 for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16) 1727 1727 { 1728 - h1 = (signed16)(v1 & 0xffff); 1729 - h2 = (signed16)(v2 & 0xffff); 1728 + h1 = (int16_t)(v1 & 0xffff); 1729 + h2 = (int16_t)(v2 & 0xffff); 1730 1730 mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); 1731 1731 DSPCR &= mask; 1732 1732 if (op == 0) // EQ ··· 1784 1784 :function:::void:do_w_extr:int rt, int ac, int shift, int op 1785 1785 { 1786 1786 int i; 1787 - unsigned32 lo = DSPLO(ac); 1788 - unsigned32 hi = DSPHI(ac); 1789 - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; 1790 - signed64 result = (signed64)prod; 1787 + uint32_t lo = DSPLO(ac); 1788 + uint32_t hi = DSPHI(ac); 1789 + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; 1790 + int64_t result = (int64_t)prod; 1791 1791 int setcond = 0; 1792 1792 if (!(prod & 0x8000000000000000LL)) 1793 1793 { 1794 1794 for (i = 62; i >= (shift + 31); i--) 1795 1795 { 1796 - if (prod & ((unsigned64)1 << i)) 1796 + if (prod & ((uint64_t)1 << i)) 1797 1797 { 1798 1798 DSPCR |= DSPCR_OUFLAG7; 1799 1799 setcond = 1; ··· 1810 1810 { 1811 1811 for (i = 62; i >= (shift + 31); i--) 1812 1812 { 1813 - if (!(prod & ((unsigned64)1 << i))) 1813 + if (!(prod & ((uint64_t)1 << i))) 1814 1814 { 1815 1815 DSPCR |= DSPCR_OUFLAG7; 1816 1816 setcond = 2; ··· 1889 1889 :function:::void:do_h_extr:int rt, int ac, int shift 1890 1890 { 1891 1891 int i; 1892 - unsigned32 lo = DSPLO(ac); 1893 - unsigned32 hi = DSPHI(ac); 1894 - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; 1895 - signed64 result = (signed64)prod; 1896 - signed64 value = 0xffffffffffff8000LL; 1892 + uint32_t lo = DSPLO(ac); 1893 + uint32_t hi = DSPHI(ac); 1894 + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; 1895 + int64_t result = (int64_t)prod; 1896 + int64_t value = 0xffffffffffff8000LL; 1897 1897 result >>= shift; 1898 1898 if (result > 0x7fff) 1899 1899 { ··· 1925 1925 // op: 0 = EXTP, 1 = EXTPDP 1926 1926 :function:::void:do_extp:int rt, int ac, int size, int op 1927 1927 { 1928 - signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 1929 - unsigned32 lo = DSPLO(ac); 1930 - unsigned32 hi = DSPHI(ac); 1931 - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; 1932 - unsigned64 result = 0; 1928 + int32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 1929 + uint32_t lo = DSPLO(ac); 1930 + uint32_t hi = DSPHI(ac); 1931 + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; 1932 + uint64_t result = 0; 1933 1933 if (pos - (size + 1) >= -1) 1934 1934 { 1935 1935 prod >>= (pos - size); 1936 - result = prod & (((unsigned64)1 << (size + 1)) - 1); 1936 + result = prod & (((uint64_t)1 << (size + 1)) - 1); 1937 1937 DSPCR &= (~DSPCR_EFI_SMASK); 1938 1938 if (op == 1) // EXTPDP 1939 1939 { ··· 1986 1986 1987 1987 :function:::void:do_shilo:int ac, int shift 1988 1988 { 1989 - unsigned32 lo = DSPLO(ac); 1990 - unsigned32 hi = DSPHI(ac); 1991 - unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo; 1989 + uint32_t lo = DSPLO(ac); 1990 + uint32_t hi = DSPHI(ac); 1991 + uint64_t prod = (((uint64_t)hi) << 32) + (uint64_t)lo; 1992 1992 if (shift > 31) 1993 1993 shift = shift - 64; 1994 1994 if (shift >= 0) ··· 2061 2061 "bposge32 <OFFSET>" 2062 2062 *dsp: 2063 2063 { 2064 - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 2064 + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 2065 2065 address_word offset = EXTEND16 (OFFSET) << 2; 2066 2066 if (pos >= 32) 2067 2067 {
+108 -108
sim/mips/dsp2.igen
··· 26 26 :function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat 27 27 { 28 28 int i; 29 - unsigned32 h0; 30 - unsigned16 h1, h2; 31 - unsigned32 v1 = GPR[rs]; 32 - unsigned32 v2 = GPR[rt]; 33 - unsigned32 result = 0; 29 + uint32_t h0; 30 + uint16_t h1, h2; 31 + uint32_t v1 = GPR[rs]; 32 + uint32_t v2 = GPR[rt]; 33 + uint32_t result = 0; 34 34 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 35 35 { 36 - h1 = (unsigned16)(v1 & 0xffff); 37 - h2 = (unsigned16)(v2 & 0xffff); 36 + h1 = (uint16_t)(v1 & 0xffff); 37 + h2 = (uint16_t)(v2 & 0xffff); 38 38 if (op == 0) // ADD 39 - h0 = (unsigned32)h1 + (unsigned32)h2; 39 + h0 = (uint32_t)h1 + (uint32_t)h2; 40 40 else // SUB 41 - h0 = (unsigned32)h1 - (unsigned32)h2; 42 - if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT 41 + h0 = (uint32_t)h1 - (uint32_t)h2; 42 + if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT 43 43 { 44 44 DSPCR |= DSPCR_OUFLAG4; 45 45 if (sat == 1) ··· 51 51 if (sat == 1) 52 52 h0 = 0x0; 53 53 } 54 - result |= ((unsigned32)((unsigned16)h0) << i); 54 + result |= ((uint32_t)((uint16_t)h0) << i); 55 55 } 56 56 GPR[rd] = EXTEND32 (result); 57 57 } ··· 61 61 :function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round 62 62 { 63 63 int i; 64 - unsigned32 h0; 65 - unsigned8 h1, h2; 66 - unsigned32 v1 = GPR[rs]; 67 - unsigned32 v2 = GPR[rt]; 68 - unsigned32 result = 0; 64 + uint32_t h0; 65 + uint8_t h1, h2; 66 + uint32_t v1 = GPR[rs]; 67 + uint32_t v2 = GPR[rt]; 68 + uint32_t result = 0; 69 69 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) 70 70 { 71 - h1 = (unsigned8)(v1 & 0xff); 72 - h2 = (unsigned8)(v2 & 0xff); 71 + h1 = (uint8_t)(v1 & 0xff); 72 + h2 = (uint8_t)(v2 & 0xff); 73 73 if (op == 0) // ADD 74 - h0 = (unsigned32)h1 + (unsigned32)h2; 74 + h0 = (uint32_t)h1 + (uint32_t)h2; 75 75 else // SUB 76 - h0 = (unsigned32)h1 - (unsigned32)h2; 76 + h0 = (uint32_t)h1 - (uint32_t)h2; 77 77 if (round == 1) 78 78 h0 = (h0 + 1) >> 1; 79 79 else 80 80 h0 = h0 >> 1; 81 - result |= ((unsigned32)((unsigned8)h0) << i); 81 + result |= ((uint32_t)((uint8_t)h0) << i); 82 82 } 83 83 GPR[rd] = EXTEND32 (result); 84 84 } ··· 87 87 :function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op 88 88 { 89 89 int i, j; 90 - unsigned32 v1 = GPR[rs]; 91 - unsigned32 v2 = GPR[rt]; 92 - unsigned8 h1, h2; 93 - unsigned32 result = 0; 94 - unsigned32 mask; 90 + uint32_t v1 = GPR[rs]; 91 + uint32_t v2 = GPR[rt]; 92 + uint8_t h1, h2; 93 + uint32_t result = 0; 94 + uint32_t mask; 95 95 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 96 96 { 97 - h1 = (unsigned8)(v1 & 0xff); 98 - h2 = (unsigned8)(v2 & 0xff); 97 + h1 = (uint8_t)(v1 & 0xff); 98 + h2 = (uint8_t)(v2 & 0xff); 99 99 mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); 100 100 DSPCR &= mask; 101 101 if (op == 0) // EQ ··· 121 121 :function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op 122 122 { 123 123 int i; 124 - unsigned32 v1 = GPR[rs]; 125 - unsigned32 v2 = GPR[rt]; 126 - signed16 h1, h2; 127 - signed32 result; 128 - unsigned32 lo = DSPLO(ac); 129 - unsigned32 hi = DSPHI(ac); 130 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 124 + uint32_t v1 = GPR[rs]; 125 + uint32_t v2 = GPR[rt]; 126 + int16_t h1, h2; 127 + int32_t result; 128 + uint32_t lo = DSPLO(ac); 129 + uint32_t hi = DSPHI(ac); 130 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 131 131 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 132 132 { 133 - h1 = (signed16)(v1 & 0xffff); 134 - h2 = (signed16)(v2 & 0xffff); 135 - result = (signed32)h1 * (signed32)h2; 133 + h1 = (int16_t)(v1 & 0xffff); 134 + h2 = (int16_t)(v2 & 0xffff); 135 + result = (int32_t)h1 * (int32_t)h2; 136 136 if (op == 0) // DPA 137 - prod += (signed64)result; 137 + prod += (int64_t)result; 138 138 else // DPS 139 - prod -= (signed64)result; 139 + prod -= (int64_t)result; 140 140 } 141 141 DSPLO(ac) = EXTEND32 (prod); 142 142 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 145 145 // round: 0 = no rounding, 1 = rounding 146 146 :function:::void:do_w_mulq:int rd, int rs, int rt, int round 147 147 { 148 - unsigned32 v1 = GPR[rs]; 149 - unsigned32 v2 = GPR[rt]; 150 - signed32 w1, w2; 151 - signed64 prod; 152 - unsigned32 result; 153 - w1 = (signed32) v1; 154 - w2 = (signed32) v2; 155 - if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000) 148 + uint32_t v1 = GPR[rs]; 149 + uint32_t v2 = GPR[rt]; 150 + int32_t w1, w2; 151 + int64_t prod; 152 + uint32_t result; 153 + w1 = (int32_t) v1; 154 + w2 = (int32_t) v2; 155 + if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000) 156 156 { 157 157 DSPCR |= DSPCR_OUFLAG5; 158 158 prod = 0x7fffffff; 159 159 } 160 160 else 161 161 { 162 - prod = ((signed64) w1 * (signed64) w2) << 1; 162 + prod = ((int64_t) w1 * (int64_t) w2) << 1; 163 163 if (round == 1) 164 164 prod += 0x0000000080000000LL; 165 165 prod = prod >> 32; 166 166 } 167 - result = (unsigned32) prod; 167 + result = (uint32_t) prod; 168 168 GPR[rd] = EXTEND32 (result); 169 169 } 170 170 171 171 // round: 0 = no rounding, 1 = rounding 172 172 :function:::void:do_precr_sra:int rt, int rs, int sa, int round 173 173 { 174 - unsigned32 v1 = GPR[rt]; 175 - unsigned32 v2 = GPR[rs]; 176 - signed32 w1 = (signed32) v1; 177 - signed32 w2 = (signed32) v2; 178 - signed32 result; 174 + uint32_t v1 = GPR[rt]; 175 + uint32_t v2 = GPR[rs]; 176 + int32_t w1 = (int32_t) v1; 177 + int32_t w2 = (int32_t) v2; 178 + int32_t result; 179 179 if (sa != 0) 180 180 { 181 181 if (round == 1 && (w1 & (1 << (sa - 1)))) ··· 196 196 :function:::void:do_qb_shra:int rd, int rt, int shift, int round 197 197 { 198 198 int i, j; 199 - signed8 q0; 200 - unsigned32 v1 = GPR[rt]; 201 - unsigned32 result = 0; 199 + int8_t q0; 200 + uint32_t v1 = GPR[rt]; 201 + uint32_t result = 0; 202 202 for (i = 0; i < 32; i += 8, v1 >>= 8) 203 203 { 204 - q0 = (signed8)(v1 & 0xff); 204 + q0 = (int8_t)(v1 & 0xff); 205 205 if (shift != 0) 206 206 { 207 207 if (round == 1 && (q0 & (1 << (shift - 1)))) ··· 209 209 else 210 210 q0 = q0 >> shift; 211 211 } 212 - result |= ((unsigned32)((unsigned8)q0) << i); 212 + result |= ((uint32_t)((uint8_t)q0) << i); 213 213 } 214 214 GPR[rd] = EXTEND32 (result); 215 215 } ··· 217 217 :function:::void:do_ph_shrl:int rd, int rt, int shift 218 218 { 219 219 int i, j; 220 - unsigned16 h0; 221 - unsigned32 v1 = GPR[rt]; 222 - unsigned32 result = 0; 220 + uint16_t h0; 221 + uint32_t v1 = GPR[rt]; 222 + uint32_t result = 0; 223 223 for (i = 0; i < 32; i += 16, v1 >>= 16) 224 224 { 225 - h0 = (unsigned16)(v1 & 0xffff); 225 + h0 = (uint16_t)(v1 & 0xffff); 226 226 h0 = h0 >> shift; 227 - result |= ((unsigned32)h0 << i); 227 + result |= ((uint32_t)h0 << i); 228 228 } 229 229 GPR[rd] = EXTEND32 (result); 230 230 } ··· 234 234 :function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round 235 235 { 236 236 int i; 237 - signed32 h0; 238 - signed16 h1, h2; 239 - unsigned32 v1 = GPR[rs]; 240 - unsigned32 v2 = GPR[rt]; 241 - unsigned32 result = 0; 237 + int32_t h0; 238 + int16_t h1, h2; 239 + uint32_t v1 = GPR[rs]; 240 + uint32_t v2 = GPR[rt]; 241 + uint32_t result = 0; 242 242 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 243 243 { 244 - h1 = (signed16)(v1 & 0xffff); 245 - h2 = (signed16)(v2 & 0xffff); 244 + h1 = (int16_t)(v1 & 0xffff); 245 + h2 = (int16_t)(v2 & 0xffff); 246 246 if (op == 0) // ADD 247 - h0 = (signed32)h1 + (signed32)h2; 247 + h0 = (int32_t)h1 + (int32_t)h2; 248 248 else // SUB 249 - h0 = (signed32)h1 - (signed32)h2; 249 + h0 = (int32_t)h1 - (int32_t)h2; 250 250 if (round == 1) 251 251 h0 = (h0 + 1) >> 1; 252 252 else 253 253 h0 = h0 >> 1; 254 - result |= ((unsigned32)((unsigned16)h0) << i); 254 + result |= ((uint32_t)((uint16_t)h0) << i); 255 255 } 256 256 GPR[rd] = EXTEND32 (result); 257 257 } ··· 261 261 :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round 262 262 { 263 263 int i; 264 - signed64 v0; 265 - signed32 v1 = (signed32)GPR[rs]; 266 - signed32 v2 = (signed32)GPR[rt]; 264 + int64_t v0; 265 + int32_t v1 = (int32_t)GPR[rs]; 266 + int32_t v2 = (int32_t)GPR[rt]; 267 267 if (op == 0) // ADD 268 - v0 = (signed64)v1 + (signed64)v2; 268 + v0 = (int64_t)v1 + (int64_t)v2; 269 269 else // SUB 270 - v0 = (signed64)v1 - (signed64)v2; 270 + v0 = (int64_t)v1 - (int64_t)v2; 271 271 if (round == 1) 272 272 v0 = (v0 + 1) >> 1; 273 273 else ··· 279 279 :function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op 280 280 { 281 281 int i; 282 - unsigned32 v1 = GPR[rs]; 283 - unsigned32 v2 = GPR[rt]; 284 - signed16 h1, h2; 285 - signed32 result; 286 - unsigned32 lo = DSPLO(ac); 287 - unsigned32 hi = DSPHI(ac); 288 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 282 + uint32_t v1 = GPR[rs]; 283 + uint32_t v2 = GPR[rt]; 284 + int16_t h1, h2; 285 + int32_t result; 286 + uint32_t lo = DSPLO(ac); 287 + uint32_t hi = DSPHI(ac); 288 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 289 289 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 290 290 { 291 - h1 = (signed16)(v1 & 0xffff); 292 - h2 = (signed16)((v2 & 0xffff0000) >> 16); 293 - result = (signed32)h1 * (signed32)h2; 291 + h1 = (int16_t)(v1 & 0xffff); 292 + h2 = (int16_t)((v2 & 0xffff0000) >> 16); 293 + result = (int32_t)h1 * (int32_t)h2; 294 294 if (op == 0) // DPAX 295 - prod += (signed64)result; 295 + prod += (int64_t)result; 296 296 else // DPSX 297 - prod -= (signed64)result; 297 + prod -= (int64_t)result; 298 298 } 299 299 DSPLO(ac) = EXTEND32 (prod); 300 300 DSPHI(ac) = EXTEND32 (prod >> 32); ··· 305 305 :function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat 306 306 { 307 307 int i; 308 - unsigned32 v1 = GPR[rs]; 309 - unsigned32 v2 = GPR[rt]; 310 - signed16 h1, h2; 311 - signed32 result; 312 - unsigned32 lo = DSPLO(ac); 313 - unsigned32 hi = DSPHI(ac); 314 - signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo); 315 - signed64 max, min; 308 + uint32_t v1 = GPR[rs]; 309 + uint32_t v2 = GPR[rt]; 310 + int16_t h1, h2; 311 + int32_t result; 312 + uint32_t lo = DSPLO(ac); 313 + uint32_t hi = DSPHI(ac); 314 + int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 315 + int64_t max, min; 316 316 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 317 317 { 318 - h1 = (signed16)(v1 & 0xffff); 319 - h2 = (signed16)((v2 & 0xffff0000) >> 16); 320 - if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000) 318 + h1 = (int16_t)(v1 & 0xffff); 319 + h2 = (int16_t)((v2 & 0xffff0000) >> 16); 320 + if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 321 321 { 322 322 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 323 323 result = 0x7fffffff; 324 324 } 325 325 else 326 - result = ((signed32)h1 * (signed32)h2) << 1; 326 + result = ((int32_t)h1 * (int32_t)h2) << 1; 327 327 if (op == 0) // DPAQX 328 - prod += (signed64)result; 328 + prod += (int64_t)result; 329 329 else // DPSQX 330 - prod -= (signed64)result; 330 + prod -= (int64_t)result; 331 331 } 332 332 // Saturation on the accumulator. 333 333 if (sat == 1) 334 334 { 335 - max = (signed64) 0x7fffffffLL; 336 - min = (signed64) 0xffffffff80000000LL; 335 + max = (int64_t) 0x7fffffffLL; 336 + min = (int64_t) 0xffffffff80000000LL; 337 337 if (prod > max) 338 338 { 339 339 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
+25 -25
sim/mips/interp.c
··· 718 718 for (loop = 0; (loop < idt_monitor_size); loop += 4) 719 719 { 720 720 address_word vaddr = (idt_monitor_base + loop); 721 - unsigned32 insn = (RSVD_INSTRUCTION | 721 + uint32_t insn = (RSVD_INSTRUCTION | 722 722 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) 723 723 << RSVD_INSTRUCTION_ARG_SHIFT)); 724 724 H2T (insn); ··· 737 737 unsigned loop; 738 738 for (loop = 0; (loop < 24); loop++) 739 739 { 740 - unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ 740 + uint32_t value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */ 741 741 switch (loop) 742 742 { 743 743 case 0: /* read */ ··· 787 787 (pmon_monitor_base != 0) || 788 788 (lsipmon_monitor_base != 0)) 789 789 { 790 - unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, 790 + uint32_t halt[2] = { 0x2404002f /* addiu r4, r0, 47 */, 791 791 HALT_INSTRUCTION /* BREAK */ }; 792 792 H2T (halt[0]); 793 793 H2T (halt[1]); ··· 869 869 if (length == 8) 870 870 { 871 871 cpu->fgr[rn - FGR_BASE] = 872 - (unsigned32) T2H_8 (*(unsigned64*)memory); 872 + (uint32_t) T2H_8 (*(uint64_t*)memory); 873 873 return 8; 874 874 } 875 875 else 876 876 { 877 - cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory); 877 + cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory); 878 878 return 4; 879 879 } 880 880 } ··· 882 882 { 883 883 if (length == 8) 884 884 { 885 - cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory); 885 + cpu->fgr[rn - FGR_BASE] = T2H_8 (*(uint64_t*)memory); 886 886 return 8; 887 887 } 888 888 else 889 889 { 890 - cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory); 890 + cpu->fgr[rn - FGR_BASE] = T2H_4 (*(uint32_t*)memory); 891 891 return 4; 892 892 } 893 893 } ··· 898 898 if (length == 8) 899 899 { 900 900 cpu->registers[rn] = 901 - (unsigned32) T2H_8 (*(unsigned64*)memory); 901 + (uint32_t) T2H_8 (*(uint64_t*)memory); 902 902 return 8; 903 903 } 904 904 else 905 905 { 906 - cpu->registers[rn] = T2H_4 (*(unsigned32*)memory); 906 + cpu->registers[rn] = T2H_4 (*(uint32_t*)memory); 907 907 return 4; 908 908 } 909 909 } ··· 911 911 { 912 912 if (length == 8) 913 913 { 914 - cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); 914 + cpu->registers[rn] = T2H_8 (*(uint64_t*)memory); 915 915 return 8; 916 916 } 917 917 else 918 918 { 919 - cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory); 919 + cpu->registers[rn] = (int32_t) T2H_4(*(uint32_t*)memory); 920 920 return 4; 921 921 } 922 922 } ··· 943 943 { 944 944 if (length == 8) 945 945 { 946 - *(unsigned64*)memory = 947 - H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE])); 946 + *(uint64_t*)memory = 947 + H2T_8 ((uint32_t) (cpu->fgr[rn - FGR_BASE])); 948 948 return 8; 949 949 } 950 950 else 951 951 { 952 - *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]); 952 + *(uint32_t*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]); 953 953 return 4; 954 954 } 955 955 } ··· 957 957 { 958 958 if (length == 8) 959 959 { 960 - *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]); 960 + *(uint64_t*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]); 961 961 return 8; 962 962 } 963 963 else 964 964 { 965 - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE])); 965 + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->fgr[rn - FGR_BASE])); 966 966 return 4; 967 967 } 968 968 } ··· 972 972 { 973 973 if (length == 8) 974 974 { 975 - *(unsigned64*)memory = 976 - H2T_8 ((unsigned32) (cpu->registers[rn])); 975 + *(uint64_t*)memory = 976 + H2T_8 ((uint32_t) (cpu->registers[rn])); 977 977 return 8; 978 978 } 979 979 else 980 980 { 981 - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); 981 + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn])); 982 982 return 4; 983 983 } 984 984 } ··· 986 986 { 987 987 if (length == 8) 988 988 { 989 - *(unsigned64*)memory = 990 - H2T_8 ((unsigned64) (cpu->registers[rn])); 989 + *(uint64_t*)memory = 990 + H2T_8 ((uint64_t) (cpu->registers[rn])); 991 991 return 8; 992 992 } 993 993 else 994 994 { 995 - *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn])); 995 + *(uint32_t*)memory = H2T_4 ((uint32_t)(cpu->registers[rn])); 996 996 return 4; 997 997 } 998 998 } ··· 1028 1028 These addresses work as is on 64-bit targets but 1029 1029 can be truncated for 32-bit targets. */ 1030 1030 if (WITH_TARGET_WORD_BITSIZE == 32) 1031 - pc = (unsigned32) pc; 1031 + pc = (uint32_t) pc; 1032 1032 1033 1033 CPU_PC_SET (cpu, pc); 1034 1034 } ··· 2321 2321 /* CPR[0,rd] = GPR[rt]; */ 2322 2322 default: 2323 2323 if (op == cp0_mfc0 || op == cp0_dmfc0) 2324 - GPR[rt] = (signed_word) (signed32) COP0_GPR[rd]; 2324 + GPR[rt] = (signed_word) (int32_t) COP0_GPR[rd]; 2325 2325 else 2326 2326 COP0_GPR[rd] = GPR[rt]; 2327 2327 #if 0 ··· 2336 2336 && rd == 16) 2337 2337 { 2338 2338 /* [D]MFC0 RT,C0_CONFIG,SEL */ 2339 - signed32 cfg = 0; 2339 + int32_t cfg = 0; 2340 2340 switch (sel) 2341 2341 { 2342 2342 case 0:
+2 -2
sim/mips/m16.igen
··· 454 454 *mips16: 455 455 *vr4100: 456 456 { 457 - unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2); 457 + uint32_t temp = (basepc (SD_) & ~3) + (IMMED << 2); 458 458 GPR[TRX] = EXTEND32 (temp); 459 459 } 460 460 ··· 463 463 *mips16: 464 464 *vr4100: 465 465 { 466 - unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); 466 + uint32_t temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE); 467 467 GPR[TRX] = EXTEND32 (temp); 468 468 } 469 469
+3 -3
sim/mips/m16e.igen
··· 55 55 *mips16e: 56 56 { 57 57 TRACE_ALU_INPUT1 (GPR[TRX]); 58 - GPR[TRX] = (unsigned_word)(unsigned8)(GPR[TRX]); 58 + GPR[TRX] = (unsigned_word)(uint8_t)(GPR[TRX]); 59 59 TRACE_ALU_RESULT (GPR[TRX]); 60 60 } 61 61 ··· 64 64 *mips16e: 65 65 { 66 66 TRACE_ALU_INPUT1 (GPR[TRX]); 67 - GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]); 67 + GPR[TRX] = (unsigned_word)(uint16_t)(GPR[TRX]); 68 68 TRACE_ALU_RESULT (GPR[TRX]); 69 69 } 70 70 ··· 74 74 { 75 75 check_u64 (SD_, instruction_0); 76 76 TRACE_ALU_INPUT1 (GPR[TRX]); 77 - GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]); 77 + GPR[TRX] = (unsigned_word)(uint32_t)(GPR[TRX]); 78 78 TRACE_ALU_RESULT (GPR[TRX]); 79 79 } 80 80
+258 -258
sim/mips/mdmx.c
··· 54 54 the (not guaranteed portable) assumption that right shifts of signed 55 55 quantities in C do sign extension. */ 56 56 57 - typedef unsigned64 unsigned48; 57 + typedef uint64_t unsigned48; 58 58 #define MASK48 (UNSIGNED64 (0xffffffffffff)) 59 59 60 - typedef unsigned32 unsigned24; 60 + typedef uint32_t unsigned24; 61 61 #define MASK24 (UNSIGNED32 (0xffffff)) 62 62 63 63 typedef enum { ··· 71 71 sel_imm /* immediate select */ 72 72 } VT_select; 73 73 74 - #define OB_MAX ((unsigned8)0xFF) 75 - #define QH_MIN ((signed16)0x8000) 76 - #define QH_MAX ((signed16)0x7FFF) 74 + #define OB_MAX ((uint8_t)0xFF) 75 + #define QH_MIN ((int16_t)0x8000) 76 + #define QH_MAX ((int16_t)0x7FFF) 77 77 78 - #define OB_CLAMP(x) ((unsigned8)((x) > OB_MAX ? OB_MAX : (x))) 79 - #define QH_CLAMP(x) ((signed16)((x) < QH_MIN ? QH_MIN : \ 78 + #define OB_CLAMP(x) ((uint8_t)((x) > OB_MAX ? OB_MAX : (x))) 79 + #define QH_CLAMP(x) ((int16_t)((x) < QH_MIN ? QH_MIN : \ 80 80 ((x) > QH_MAX ? QH_MAX : (x)))) 81 81 82 82 #define MX_FMT(fmtsel) (((fmtsel) & 0x1) == 0 ? mdmx_ob : mdmx_qh) ··· 84 84 (((fmtsel) & 0x18) == 0x10 ? sel_vect : sel_imm)) 85 85 86 86 #define QH_ELEM(v,fmtsel) \ 87 - ((signed16)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF)) 87 + ((int16_t)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF)) 88 88 #define OB_ELEM(v,fmtsel) \ 89 - ((unsigned8)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF)) 89 + ((uint8_t)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF)) 90 90 91 91 92 - typedef signed16 (*QH_FUNC)(signed16, signed16); 93 - typedef unsigned8 (*OB_FUNC)(unsigned8, unsigned8); 92 + typedef int16_t (*QH_FUNC)(int16_t, int16_t); 93 + typedef uint8_t (*OB_FUNC)(uint8_t, uint8_t); 94 94 95 95 /* vectorized logical operators */ 96 96 97 - static signed16 98 - AndQH(signed16 ts, signed16 tt) 97 + static int16_t 98 + AndQH(int16_t ts, int16_t tt) 99 99 { 100 - return (signed16)((unsigned16)ts & (unsigned16)tt); 100 + return (int16_t)((uint16_t)ts & (uint16_t)tt); 101 101 } 102 102 103 - static unsigned8 104 - AndOB(unsigned8 ts, unsigned8 tt) 103 + static uint8_t 104 + AndOB(uint8_t ts, uint8_t tt) 105 105 { 106 106 return ts & tt; 107 107 } 108 108 109 - static signed16 110 - NorQH(signed16 ts, signed16 tt) 109 + static int16_t 110 + NorQH(int16_t ts, int16_t tt) 111 111 { 112 - return (signed16)(((unsigned16)ts | (unsigned16)tt) ^ 0xFFFF); 112 + return (int16_t)(((uint16_t)ts | (uint16_t)tt) ^ 0xFFFF); 113 113 } 114 114 115 - static unsigned8 116 - NorOB(unsigned8 ts, unsigned8 tt) 115 + static uint8_t 116 + NorOB(uint8_t ts, uint8_t tt) 117 117 { 118 118 return (ts | tt) ^ 0xFF; 119 119 } 120 120 121 - static signed16 122 - OrQH(signed16 ts, signed16 tt) 121 + static int16_t 122 + OrQH(int16_t ts, int16_t tt) 123 123 { 124 - return (signed16)((unsigned16)ts | (unsigned16)tt); 124 + return (int16_t)((uint16_t)ts | (uint16_t)tt); 125 125 } 126 126 127 - static unsigned8 128 - OrOB(unsigned8 ts, unsigned8 tt) 127 + static uint8_t 128 + OrOB(uint8_t ts, uint8_t tt) 129 129 { 130 130 return ts | tt; 131 131 } 132 132 133 - static signed16 134 - XorQH(signed16 ts, signed16 tt) 133 + static int16_t 134 + XorQH(int16_t ts, int16_t tt) 135 135 { 136 - return (signed16)((unsigned16)ts ^ (unsigned16)tt); 136 + return (int16_t)((uint16_t)ts ^ (uint16_t)tt); 137 137 } 138 138 139 - static unsigned8 140 - XorOB(unsigned8 ts, unsigned8 tt) 139 + static uint8_t 140 + XorOB(uint8_t ts, uint8_t tt) 141 141 { 142 142 return ts ^ tt; 143 143 } 144 144 145 - static signed16 146 - SLLQH(signed16 ts, signed16 tt) 145 + static int16_t 146 + SLLQH(int16_t ts, int16_t tt) 147 147 { 148 - unsigned32 s = (unsigned32)tt & 0xF; 149 - return (signed16)(((unsigned32)ts << s) & 0xFFFF); 148 + uint32_t s = (uint32_t)tt & 0xF; 149 + return (int16_t)(((uint32_t)ts << s) & 0xFFFF); 150 150 } 151 151 152 - static unsigned8 153 - SLLOB(unsigned8 ts, unsigned8 tt) 152 + static uint8_t 153 + SLLOB(uint8_t ts, uint8_t tt) 154 154 { 155 - unsigned32 s = tt & 0x7; 155 + uint32_t s = tt & 0x7; 156 156 return (ts << s) & 0xFF; 157 157 } 158 158 159 - static signed16 160 - SRLQH(signed16 ts, signed16 tt) 159 + static int16_t 160 + SRLQH(int16_t ts, int16_t tt) 161 161 { 162 - unsigned32 s = (unsigned32)tt & 0xF; 163 - return (signed16)((unsigned16)ts >> s); 162 + uint32_t s = (uint32_t)tt & 0xF; 163 + return (int16_t)((uint16_t)ts >> s); 164 164 } 165 165 166 - static unsigned8 167 - SRLOB(unsigned8 ts, unsigned8 tt) 166 + static uint8_t 167 + SRLOB(uint8_t ts, uint8_t tt) 168 168 { 169 - unsigned32 s = tt & 0x7; 169 + uint32_t s = tt & 0x7; 170 170 return ts >> s; 171 171 } 172 172 173 173 174 174 /* Vectorized arithmetic operators. */ 175 175 176 - static signed16 177 - AddQH(signed16 ts, signed16 tt) 176 + static int16_t 177 + AddQH(int16_t ts, int16_t tt) 178 178 { 179 - signed32 t = (signed32)ts + (signed32)tt; 179 + int32_t t = (int32_t)ts + (int32_t)tt; 180 180 return QH_CLAMP(t); 181 181 } 182 182 183 - static unsigned8 184 - AddOB(unsigned8 ts, unsigned8 tt) 183 + static uint8_t 184 + AddOB(uint8_t ts, uint8_t tt) 185 185 { 186 - unsigned32 t = (unsigned32)ts + (unsigned32)tt; 186 + uint32_t t = (uint32_t)ts + (uint32_t)tt; 187 187 return OB_CLAMP(t); 188 188 } 189 189 190 - static signed16 191 - SubQH(signed16 ts, signed16 tt) 190 + static int16_t 191 + SubQH(int16_t ts, int16_t tt) 192 192 { 193 - signed32 t = (signed32)ts - (signed32)tt; 193 + int32_t t = (int32_t)ts - (int32_t)tt; 194 194 return QH_CLAMP(t); 195 195 } 196 196 197 - static unsigned8 198 - SubOB(unsigned8 ts, unsigned8 tt) 197 + static uint8_t 198 + SubOB(uint8_t ts, uint8_t tt) 199 199 { 200 - signed32 t; 201 - t = (signed32)ts - (signed32)tt; 200 + int32_t t; 201 + t = (int32_t)ts - (int32_t)tt; 202 202 if (t < 0) 203 203 t = 0; 204 - return (unsigned8)t; 204 + return (uint8_t)t; 205 205 } 206 206 207 - static signed16 208 - MinQH(signed16 ts, signed16 tt) 207 + static int16_t 208 + MinQH(int16_t ts, int16_t tt) 209 209 { 210 210 return (ts < tt ? ts : tt); 211 211 } 212 212 213 - static unsigned8 214 - MinOB(unsigned8 ts, unsigned8 tt) 213 + static uint8_t 214 + MinOB(uint8_t ts, uint8_t tt) 215 215 { 216 216 return (ts < tt ? ts : tt); 217 217 } 218 218 219 - static signed16 220 - MaxQH(signed16 ts, signed16 tt) 219 + static int16_t 220 + MaxQH(int16_t ts, int16_t tt) 221 221 { 222 222 return (ts > tt ? ts : tt); 223 223 } 224 224 225 - static unsigned8 226 - MaxOB(unsigned8 ts, unsigned8 tt) 225 + static uint8_t 226 + MaxOB(uint8_t ts, uint8_t tt) 227 227 { 228 228 return (ts > tt ? ts : tt); 229 229 } 230 230 231 - static signed16 232 - MulQH(signed16 ts, signed16 tt) 231 + static int16_t 232 + MulQH(int16_t ts, int16_t tt) 233 233 { 234 - signed32 t = (signed32)ts * (signed32)tt; 234 + int32_t t = (int32_t)ts * (int32_t)tt; 235 235 return QH_CLAMP(t); 236 236 } 237 237 238 - static unsigned8 239 - MulOB(unsigned8 ts, unsigned8 tt) 238 + static uint8_t 239 + MulOB(uint8_t ts, uint8_t tt) 240 240 { 241 - unsigned32 t = (unsigned32)ts * (unsigned32)tt; 241 + uint32_t t = (uint32_t)ts * (uint32_t)tt; 242 242 return OB_CLAMP(t); 243 243 } 244 244 245 245 /* "msgn" and "sra" are defined only for QH format. */ 246 246 247 - static signed16 248 - MsgnQH(signed16 ts, signed16 tt) 247 + static int16_t 248 + MsgnQH(int16_t ts, int16_t tt) 249 249 { 250 - signed16 t; 250 + int16_t t; 251 251 if (ts < 0) 252 252 t = (tt == QH_MIN ? QH_MAX : -tt); 253 253 else if (ts == 0) ··· 257 257 return t; 258 258 } 259 259 260 - static signed16 261 - SRAQH(signed16 ts, signed16 tt) 260 + static int16_t 261 + SRAQH(int16_t ts, int16_t tt) 262 262 { 263 - unsigned32 s = (unsigned32)tt & 0xF; 264 - return (signed16)((signed32)ts >> s); 263 + uint32_t s = (uint32_t)tt & 0xF; 264 + return (int16_t)((int32_t)ts >> s); 265 265 } 266 266 267 267 268 268 /* "pabsdiff" and "pavg" are defined only for OB format. */ 269 269 270 - static unsigned8 271 - AbsDiffOB(unsigned8 ts, unsigned8 tt) 270 + static uint8_t 271 + AbsDiffOB(uint8_t ts, uint8_t tt) 272 272 { 273 273 return (ts >= tt ? ts - tt : tt - ts); 274 274 } 275 275 276 - static unsigned8 277 - AvgOB(unsigned8 ts, unsigned8 tt) 276 + static uint8_t 277 + AvgOB(uint8_t ts, uint8_t tt) 278 278 { 279 - return ((unsigned32)ts + (unsigned32)tt + 1) >> 1; 279 + return ((uint32_t)ts + (uint32_t)tt + 1) >> 1; 280 280 } 281 281 282 282 ··· 297 297 /* Auxiliary functions for CPR updates. */ 298 298 299 299 /* Vector mapping for QH format. */ 300 - static unsigned64 301 - qh_vector_op(unsigned64 v1, unsigned64 v2, QH_FUNC func) 300 + static uint64_t 301 + qh_vector_op(uint64_t v1, uint64_t v2, QH_FUNC func) 302 302 { 303 - unsigned64 result = 0; 303 + uint64_t result = 0; 304 304 int i; 305 - signed16 h, h1, h2; 305 + int16_t h, h1, h2; 306 306 307 307 for (i = 0; i < 64; i += 16) 308 308 { 309 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 310 - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; 309 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 310 + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; 311 311 h = (*func)(h1, h2); 312 - result |= ((unsigned64)((unsigned16)h) << i); 312 + result |= ((uint64_t)((uint16_t)h) << i); 313 313 } 314 314 return result; 315 315 } 316 316 317 - static unsigned64 318 - qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func) 317 + static uint64_t 318 + qh_map_op(uint64_t v1, int16_t h2, QH_FUNC func) 319 319 { 320 - unsigned64 result = 0; 320 + uint64_t result = 0; 321 321 int i; 322 - signed16 h, h1; 322 + int16_t h, h1; 323 323 324 324 for (i = 0; i < 64; i += 16) 325 325 { 326 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 326 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 327 327 h = (*func)(h1, h2); 328 - result |= ((unsigned64)((unsigned16)h) << i); 328 + result |= ((uint64_t)((uint16_t)h) << i); 329 329 } 330 330 return result; 331 331 } ··· 333 333 334 334 /* Vector operations for OB format. */ 335 335 336 - static unsigned64 337 - ob_vector_op(unsigned64 v1, unsigned64 v2, OB_FUNC func) 336 + static uint64_t 337 + ob_vector_op(uint64_t v1, uint64_t v2, OB_FUNC func) 338 338 { 339 - unsigned64 result = 0; 339 + uint64_t result = 0; 340 340 int i; 341 - unsigned8 b, b1, b2; 341 + uint8_t b, b1, b2; 342 342 343 343 for (i = 0; i < 64; i += 8) 344 344 { 345 345 b1 = v1 & 0xFF; v1 >>= 8; 346 346 b2 = v2 & 0xFF; v2 >>= 8; 347 347 b = (*func)(b1, b2); 348 - result |= ((unsigned64)b << i); 348 + result |= ((uint64_t)b << i); 349 349 } 350 350 return result; 351 351 } 352 352 353 - static unsigned64 354 - ob_map_op(unsigned64 v1, unsigned8 b2, OB_FUNC func) 353 + static uint64_t 354 + ob_map_op(uint64_t v1, uint8_t b2, OB_FUNC func) 355 355 { 356 - unsigned64 result = 0; 356 + uint64_t result = 0; 357 357 int i; 358 - unsigned8 b, b1; 358 + uint8_t b, b1; 359 359 360 360 for (i = 0; i < 64; i += 8) 361 361 { 362 362 b1 = v1 & 0xFF; v1 >>= 8; 363 363 b = (*func)(b1, b2); 364 - result |= ((unsigned64)b << i); 364 + result |= ((uint64_t)b << i); 365 365 } 366 366 return result; 367 367 } 368 368 369 369 370 370 /* Primary entry for operations that update CPRs. */ 371 - unsigned64 371 + uint64_t 372 372 mdmx_cpr_op(sim_cpu *cpu, 373 373 address_word cia, 374 374 int op, 375 - unsigned64 op1, 375 + uint64_t op1, 376 376 int vt, 377 377 MX_fmtsel fmtsel) 378 378 { 379 - unsigned64 op2; 380 - unsigned64 result = 0; 379 + uint64_t op2; 380 + uint64_t result = 0; 381 381 382 382 switch (MX_FMT (fmtsel)) 383 383 { ··· 422 422 /* Operations that update CCs */ 423 423 424 424 static void 425 - qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) 425 + qh_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond) 426 426 { 427 427 int i; 428 - signed16 h1, h2; 428 + int16_t h1, h2; 429 429 int boolean; 430 430 431 431 for (i = 0; i < 4; i++) 432 432 { 433 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 434 - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; 433 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 434 + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; 435 435 boolean = ((cond & MX_C_EQ) && (h1 == h2)) || 436 436 ((cond & MX_C_LT) && (h1 < h2)); 437 437 SETFCC(i, boolean); ··· 439 439 } 440 440 441 441 static void 442 - qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond) 442 + qh_map_test(sim_cpu *cpu, uint64_t v1, int16_t h2, int cond) 443 443 { 444 444 int i; 445 - signed16 h1; 445 + int16_t h1; 446 446 int boolean; 447 447 448 448 for (i = 0; i < 4; i++) 449 449 { 450 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 450 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 451 451 boolean = ((cond & MX_C_EQ) && (h1 == h2)) || 452 452 ((cond & MX_C_LT) && (h1 < h2)); 453 453 SETFCC(i, boolean); ··· 455 455 } 456 456 457 457 static void 458 - ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond) 458 + ob_vector_test(sim_cpu *cpu, uint64_t v1, uint64_t v2, int cond) 459 459 { 460 460 int i; 461 - unsigned8 b1, b2; 461 + uint8_t b1, b2; 462 462 int boolean; 463 463 464 464 for (i = 0; i < 8; i++) ··· 472 472 } 473 473 474 474 static void 475 - ob_map_test(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int cond) 475 + ob_map_test(sim_cpu *cpu, uint64_t v1, uint8_t b2, int cond) 476 476 { 477 477 int i; 478 - unsigned8 b1; 478 + uint8_t b1; 479 479 int boolean; 480 480 481 481 for (i = 0; i < 8; i++) 482 482 { 483 - b1 = (unsigned8)(v1 & 0xFF); v1 >>= 8; 483 + b1 = (uint8_t)(v1 & 0xFF); v1 >>= 8; 484 484 boolean = ((cond & MX_C_EQ) && (b1 == b2)) || 485 485 ((cond & MX_C_LT) && (b1 < b2)); 486 486 SETFCC(i, boolean); ··· 492 492 mdmx_cc_op(sim_cpu *cpu, 493 493 address_word cia, 494 494 int cond, 495 - unsigned64 v1, 495 + uint64_t v1, 496 496 int vt, 497 497 MX_fmtsel fmtsel) 498 498 { 499 - unsigned64 op2; 499 + uint64_t op2; 500 500 501 501 switch (MX_FMT (fmtsel)) 502 502 { ··· 538 538 539 539 /* Pick operations. */ 540 540 541 - static unsigned64 542 - qh_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) 541 + static uint64_t 542 + qh_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf) 543 543 { 544 - unsigned64 result = 0; 544 + uint64_t result = 0; 545 545 int i, s; 546 - unsigned16 h; 546 + uint16_t h; 547 547 548 548 s = 0; 549 549 for (i = 0; i < 4; i++) 550 550 { 551 551 h = ((GETFCC(i) == tf) ? (v1 & 0xFFFF) : (v2 & 0xFFFF)); 552 552 v1 >>= 16; v2 >>= 16; 553 - result |= ((unsigned64)h << s); 553 + result |= ((uint64_t)h << s); 554 554 s += 16; 555 555 } 556 556 return result; 557 557 } 558 558 559 - static unsigned64 560 - qh_map_pick(sim_cpu *cpu, unsigned64 v1, signed16 h2, int tf) 559 + static uint64_t 560 + qh_map_pick(sim_cpu *cpu, uint64_t v1, int16_t h2, int tf) 561 561 { 562 - unsigned64 result = 0; 562 + uint64_t result = 0; 563 563 int i, s; 564 - unsigned16 h; 564 + uint16_t h; 565 565 566 566 s = 0; 567 567 for (i = 0; i < 4; i++) 568 568 { 569 - h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (unsigned16)h2; 569 + h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (uint16_t)h2; 570 570 v1 >>= 16; 571 - result |= ((unsigned64)h << s); 571 + result |= ((uint64_t)h << s); 572 572 s += 16; 573 573 } 574 574 return result; 575 575 } 576 576 577 - static unsigned64 578 - ob_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf) 577 + static uint64_t 578 + ob_vector_pick(sim_cpu *cpu, uint64_t v1, uint64_t v2, int tf) 579 579 { 580 - unsigned64 result = 0; 580 + uint64_t result = 0; 581 581 int i, s; 582 - unsigned8 b; 582 + uint8_t b; 583 583 584 584 s = 0; 585 585 for (i = 0; i < 8; i++) 586 586 { 587 587 b = (GETFCC(i) == tf) ? (v1 & 0xFF) : (v2 & 0xFF); 588 588 v1 >>= 8; v2 >>= 8; 589 - result |= ((unsigned64)b << s); 589 + result |= ((uint64_t)b << s); 590 590 s += 8; 591 591 } 592 592 return result; 593 593 } 594 594 595 - static unsigned64 596 - ob_map_pick(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int tf) 595 + static uint64_t 596 + ob_map_pick(sim_cpu *cpu, uint64_t v1, uint8_t b2, int tf) 597 597 { 598 - unsigned64 result = 0; 598 + uint64_t result = 0; 599 599 int i, s; 600 - unsigned8 b; 600 + uint8_t b; 601 601 602 602 s = 0; 603 603 for (i = 0; i < 8; i++) 604 604 { 605 605 b = (GETFCC(i) == tf) ? (v1 & 0xFF) : b2; 606 606 v1 >>= 8; 607 - result |= ((unsigned64)b << s); 607 + result |= ((uint64_t)b << s); 608 608 s += 8; 609 609 } 610 610 return result; 611 611 } 612 612 613 613 614 - unsigned64 614 + uint64_t 615 615 mdmx_pick_op(sim_cpu *cpu, 616 616 address_word cia, 617 617 int tf, 618 - unsigned64 v1, 618 + uint64_t v1, 619 619 int vt, 620 620 MX_fmtsel fmtsel) 621 621 { 622 - unsigned64 result = 0; 623 - unsigned64 op2; 622 + uint64_t result = 0; 623 + uint64_t op2; 624 624 625 625 switch (MX_FMT (fmtsel)) 626 626 { ··· 663 663 664 664 /* Accumulators. */ 665 665 666 - typedef void (*QH_ACC)(signed48 *a, signed16 ts, signed16 tt); 666 + typedef void (*QH_ACC)(signed48 *a, int16_t ts, int16_t tt); 667 667 668 668 static void 669 - AccAddAQH(signed48 *a, signed16 ts, signed16 tt) 669 + AccAddAQH(signed48 *a, int16_t ts, int16_t tt) 670 670 { 671 671 *a += (signed48)ts + (signed48)tt; 672 672 } 673 673 674 674 static void 675 - AccAddLQH(signed48 *a, signed16 ts, signed16 tt) 675 + AccAddLQH(signed48 *a, int16_t ts, int16_t tt) 676 676 { 677 677 *a = (signed48)ts + (signed48)tt; 678 678 } 679 679 680 680 static void 681 - AccMulAQH(signed48 *a, signed16 ts, signed16 tt) 681 + AccMulAQH(signed48 *a, int16_t ts, int16_t tt) 682 682 { 683 683 *a += (signed48)ts * (signed48)tt; 684 684 } 685 685 686 686 static void 687 - AccMulLQH(signed48 *a, signed16 ts, signed16 tt) 687 + AccMulLQH(signed48 *a, int16_t ts, int16_t tt) 688 688 { 689 689 *a = (signed48)ts * (signed48)tt; 690 690 } 691 691 692 692 static void 693 - SubMulAQH(signed48 *a, signed16 ts, signed16 tt) 693 + SubMulAQH(signed48 *a, int16_t ts, int16_t tt) 694 694 { 695 695 *a -= (signed48)ts * (signed48)tt; 696 696 } 697 697 698 698 static void 699 - SubMulLQH(signed48 *a, signed16 ts, signed16 tt) 699 + SubMulLQH(signed48 *a, int16_t ts, int16_t tt) 700 700 { 701 701 *a = -((signed48)ts * (signed48)tt); 702 702 } 703 703 704 704 static void 705 - AccSubAQH(signed48 *a, signed16 ts, signed16 tt) 705 + AccSubAQH(signed48 *a, int16_t ts, int16_t tt) 706 706 { 707 707 *a += (signed48)ts - (signed48)tt; 708 708 } 709 709 710 710 static void 711 - AccSubLQH(signed48 *a, signed16 ts, signed16 tt) 711 + AccSubLQH(signed48 *a, int16_t ts, int16_t tt) 712 712 { 713 713 *a = (signed48)ts - (signed48)tt; 714 714 } 715 715 716 716 717 - typedef void (*OB_ACC)(signed24 *acc, unsigned8 ts, unsigned8 tt); 717 + typedef void (*OB_ACC)(signed24 *acc, uint8_t ts, uint8_t tt); 718 718 719 719 static void 720 - AccAddAOB(signed24 *a, unsigned8 ts, unsigned8 tt) 720 + AccAddAOB(signed24 *a, uint8_t ts, uint8_t tt) 721 721 { 722 722 *a += (signed24)ts + (signed24)tt; 723 723 } 724 724 725 725 static void 726 - AccAddLOB(signed24 *a, unsigned8 ts, unsigned8 tt) 726 + AccAddLOB(signed24 *a, uint8_t ts, uint8_t tt) 727 727 { 728 728 *a = (signed24)ts + (signed24)tt; 729 729 } 730 730 731 731 static void 732 - AccMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) 732 + AccMulAOB(signed24 *a, uint8_t ts, uint8_t tt) 733 733 { 734 734 *a += (signed24)ts * (signed24)tt; 735 735 } 736 736 737 737 static void 738 - AccMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) 738 + AccMulLOB(signed24 *a, uint8_t ts, uint8_t tt) 739 739 { 740 740 *a = (signed24)ts * (signed24)tt; 741 741 } 742 742 743 743 static void 744 - SubMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt) 744 + SubMulAOB(signed24 *a, uint8_t ts, uint8_t tt) 745 745 { 746 746 *a -= (signed24)ts * (signed24)tt; 747 747 } 748 748 749 749 static void 750 - SubMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt) 750 + SubMulLOB(signed24 *a, uint8_t ts, uint8_t tt) 751 751 { 752 752 *a = -((signed24)ts * (signed24)tt); 753 753 } 754 754 755 755 static void 756 - AccSubAOB(signed24 *a, unsigned8 ts, unsigned8 tt) 756 + AccSubAOB(signed24 *a, uint8_t ts, uint8_t tt) 757 757 { 758 758 *a += (signed24)ts - (signed24)tt; 759 759 } 760 760 761 761 static void 762 - AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt) 762 + AccSubLOB(signed24 *a, uint8_t ts, uint8_t tt) 763 763 { 764 764 *a = (signed24)ts - (signed24)tt; 765 765 } 766 766 767 767 static void 768 - AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt) 768 + AccAbsDiffOB(signed24 *a, uint8_t ts, uint8_t tt) 769 769 { 770 - unsigned8 t = (ts >= tt ? ts - tt : tt - ts); 770 + uint8_t t = (ts >= tt ? ts - tt : tt - ts); 771 771 *a += (signed24)t; 772 772 } 773 773 ··· 788 788 789 789 790 790 static void 791 - qh_vector_acc(signed48 a[], unsigned64 v1, unsigned64 v2, QH_ACC acc) 791 + qh_vector_acc(signed48 a[], uint64_t v1, uint64_t v2, QH_ACC acc) 792 792 { 793 793 int i; 794 - signed16 h1, h2; 794 + int16_t h1, h2; 795 795 796 796 for (i = 0; i < 4; i++) 797 797 { 798 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 799 - h2 = (signed16)(v2 & 0xFFFF); v2 >>= 16; 798 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 799 + h2 = (int16_t)(v2 & 0xFFFF); v2 >>= 16; 800 800 (*acc)(&a[i], h1, h2); 801 801 } 802 802 } 803 803 804 804 static void 805 - qh_map_acc(signed48 a[], unsigned64 v1, signed16 h2, QH_ACC acc) 805 + qh_map_acc(signed48 a[], uint64_t v1, int16_t h2, QH_ACC acc) 806 806 { 807 807 int i; 808 - signed16 h1; 808 + int16_t h1; 809 809 810 810 for (i = 0; i < 4; i++) 811 811 { 812 - h1 = (signed16)(v1 & 0xFFFF); v1 >>= 16; 812 + h1 = (int16_t)(v1 & 0xFFFF); v1 >>= 16; 813 813 (*acc)(&a[i], h1, h2); 814 814 } 815 815 } 816 816 817 817 static void 818 - ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc) 818 + ob_vector_acc(signed24 a[], uint64_t v1, uint64_t v2, OB_ACC acc) 819 819 { 820 820 int i; 821 - unsigned8 b1, b2; 821 + uint8_t b1, b2; 822 822 823 823 for (i = 0; i < 8; i++) 824 824 { ··· 829 829 } 830 830 831 831 static void 832 - ob_map_acc(signed24 a[], unsigned64 v1, unsigned8 b2, OB_ACC acc) 832 + ob_map_acc(signed24 a[], uint64_t v1, uint8_t b2, OB_ACC acc) 833 833 { 834 834 int i; 835 - unsigned8 b1; 835 + uint8_t b1; 836 836 837 837 for (i = 0; i < 8; i++) 838 838 { ··· 847 847 mdmx_acc_op(sim_cpu *cpu, 848 848 address_word cia, 849 849 int op, 850 - unsigned64 op1, 850 + uint64_t op1, 851 851 int vt, 852 852 MX_fmtsel fmtsel) 853 853 { 854 - unsigned64 op2; 854 + uint64_t op2; 855 855 856 856 switch (MX_FMT (fmtsel)) 857 857 { ··· 893 893 894 894 /* Reading and writing accumulator (no conversion). */ 895 895 896 - unsigned64 896 + uint64_t 897 897 mdmx_rac_op(sim_cpu *cpu, 898 898 address_word cia, 899 899 int op, 900 900 int fmt) 901 901 { 902 - unsigned64 result; 902 + uint64_t result; 903 903 unsigned int shift; 904 904 int i; 905 905 ··· 934 934 mdmx_wacl(sim_cpu *cpu, 935 935 address_word cia, 936 936 int fmt, 937 - unsigned64 vs, 938 - unsigned64 vt) 937 + uint64_t vs, 938 + uint64_t vt) 939 939 { 940 940 int i; 941 941 ··· 944 944 case MX_FMT_QH: 945 945 for (i = 0; i < 4; i++) 946 946 { 947 - signed32 s = (signed16)(vs & 0xFFFF); 947 + int32_t s = (int16_t)(vs & 0xFFFF); 948 948 ACC.qh[i] = ((signed48)s << 16) | (vt & 0xFFFF); 949 949 vs >>= 16; vt >>= 16; 950 950 } ··· 952 952 case MX_FMT_OB: 953 953 for (i = 0; i < 8; i++) 954 954 { 955 - signed16 s = (signed8)(vs & 0xFF); 955 + int16_t s = (int8_t)(vs & 0xFF); 956 956 ACC.ob[i] = ((signed24)s << 8) | (vt & 0xFF); 957 957 vs >>= 8; vt >>= 8; 958 958 } ··· 966 966 mdmx_wach(sim_cpu *cpu, 967 967 address_word cia, 968 968 int fmt, 969 - unsigned64 vs) 969 + uint64_t vs) 970 970 { 971 971 int i; 972 972 ··· 975 975 case MX_FMT_QH: 976 976 for (i = 0; i < 4; i++) 977 977 { 978 - signed32 s = (signed16)(vs & 0xFFFF); 978 + int32_t s = (int16_t)(vs & 0xFFFF); 979 979 ACC.qh[i] &= ~((signed48)0xFFFF << 32); 980 980 ACC.qh[i] |= ((signed48)s << 32); 981 981 vs >>= 16; ··· 998 998 /* Reading and writing accumulator (rounding conversions). 999 999 Enumerating function guarantees s >= 0 for QH ops. */ 1000 1000 1001 - typedef signed16 (*QH_ROUND)(signed48 a, signed16 s); 1001 + typedef int16_t (*QH_ROUND)(signed48 a, int16_t s); 1002 1002 1003 1003 #define QH_BIT(n) ((unsigned48)1 << (n)) 1004 1004 #define QH_ONES(n) (((unsigned48)1 << (n))-1) 1005 1005 1006 - static signed16 1007 - RNASQH(signed48 a, signed16 s) 1006 + static int16_t 1007 + RNASQH(signed48 a, int16_t s) 1008 1008 { 1009 1009 signed48 t; 1010 - signed16 result = 0; 1010 + int16_t result = 0; 1011 1011 1012 1012 if (s > 48) 1013 1013 result = 0; ··· 1031 1031 if (t < QH_MIN) 1032 1032 t = QH_MIN; 1033 1033 } 1034 - result = (signed16)t; 1034 + result = (int16_t)t; 1035 1035 } 1036 1036 return result; 1037 1037 } 1038 1038 1039 - static signed16 1040 - RNAUQH(signed48 a, signed16 s) 1039 + static int16_t 1040 + RNAUQH(signed48 a, int16_t s) 1041 1041 { 1042 1042 unsigned48 t; 1043 - signed16 result; 1043 + int16_t result; 1044 1044 1045 1045 if (s > 48) 1046 1046 result = 0; ··· 1053 1053 t++; 1054 1054 if (t > 0xFFFF) 1055 1055 t = 0xFFFF; 1056 - result = (signed16)t; 1056 + result = (int16_t)t; 1057 1057 } 1058 1058 return result; 1059 1059 } 1060 1060 1061 - static signed16 1062 - RNESQH(signed48 a, signed16 s) 1061 + static int16_t 1062 + RNESQH(signed48 a, int16_t s) 1063 1063 { 1064 1064 signed48 t; 1065 - signed16 result = 0; 1065 + int16_t result = 0; 1066 1066 1067 1067 if (s > 47) 1068 1068 result = 0; ··· 1086 1086 if (t < QH_MIN) 1087 1087 t = QH_MIN; 1088 1088 } 1089 - result = (signed16)t; 1089 + result = (int16_t)t; 1090 1090 } 1091 1091 return result; 1092 1092 } 1093 1093 1094 - static signed16 1095 - RNEUQH(signed48 a, signed16 s) 1094 + static int16_t 1095 + RNEUQH(signed48 a, int16_t s) 1096 1096 { 1097 1097 unsigned48 t; 1098 - signed16 result; 1098 + int16_t result; 1099 1099 1100 1100 if (s > 48) 1101 1101 result = 0; ··· 1113 1113 } 1114 1114 if (t > 0xFFFF) 1115 1115 t = 0xFFFF; 1116 - result = (signed16)t; 1116 + result = (int16_t)t; 1117 1117 } 1118 1118 return result; 1119 1119 } 1120 1120 1121 - static signed16 1122 - RZSQH(signed48 a, signed16 s) 1121 + static int16_t 1122 + RZSQH(signed48 a, int16_t s) 1123 1123 { 1124 1124 signed48 t; 1125 - signed16 result = 0; 1125 + int16_t result = 0; 1126 1126 1127 1127 if (s > 47) 1128 1128 result = 0; ··· 1139 1139 if (t < QH_MIN) 1140 1140 t = QH_MIN; 1141 1141 } 1142 - result = (signed16)t; 1142 + result = (int16_t)t; 1143 1143 } 1144 1144 return result; 1145 1145 } 1146 1146 1147 - static signed16 1148 - RZUQH(signed48 a, signed16 s) 1147 + static int16_t 1148 + RZUQH(signed48 a, int16_t s) 1149 1149 { 1150 1150 unsigned48 t; 1151 - signed16 result = 0; 1151 + int16_t result = 0; 1152 1152 1153 1153 if (s > 48) 1154 1154 result = 0; ··· 1159 1159 t = ((unsigned48)a & MASK48) >> s; 1160 1160 if (t > 0xFFFF) 1161 1161 t = 0xFFFF; 1162 - result = (signed16)t; 1162 + result = (int16_t)t; 1163 1163 } 1164 1164 return result; 1165 1165 } 1166 1166 1167 1167 1168 - typedef unsigned8 (*OB_ROUND)(signed24 a, unsigned8 s); 1168 + typedef uint8_t (*OB_ROUND)(signed24 a, uint8_t s); 1169 1169 1170 1170 #define OB_BIT(n) ((unsigned24)1 << (n)) 1171 1171 #define OB_ONES(n) (((unsigned24)1 << (n))-1) 1172 1172 1173 - static unsigned8 1174 - RNAUOB(signed24 a, unsigned8 s) 1173 + static uint8_t 1174 + RNAUOB(signed24 a, uint8_t s) 1175 1175 { 1176 - unsigned8 result; 1176 + uint8_t result; 1177 1177 unsigned24 t; 1178 1178 1179 1179 if (s > 24) ··· 1190 1190 return result; 1191 1191 } 1192 1192 1193 - static unsigned8 1194 - RNEUOB(signed24 a, unsigned8 s) 1193 + static uint8_t 1194 + RNEUOB(signed24 a, uint8_t s) 1195 1195 { 1196 - unsigned8 result; 1196 + uint8_t result; 1197 1197 unsigned24 t; 1198 1198 1199 1199 if (s > 24) ··· 1215 1215 return result; 1216 1216 } 1217 1217 1218 - static unsigned8 1219 - RZUOB(signed24 a, unsigned8 s) 1218 + static uint8_t 1219 + RZUOB(signed24 a, uint8_t s) 1220 1220 { 1221 - unsigned8 result; 1221 + uint8_t result; 1222 1222 unsigned24 t; 1223 1223 1224 1224 if (s >= 24) ··· 1241 1241 }; 1242 1242 1243 1243 1244 - static unsigned64 1245 - qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round) 1244 + static uint64_t 1245 + qh_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, QH_ROUND round) 1246 1246 { 1247 - unsigned64 result = 0; 1247 + uint64_t result = 0; 1248 1248 int i, s; 1249 - signed16 h, h2; 1249 + int16_t h, h2; 1250 1250 1251 1251 s = 0; 1252 1252 for (i = 0; i < 4; i++) 1253 1253 { 1254 - h2 = (signed16)(v2 & 0xFFFF); 1254 + h2 = (int16_t)(v2 & 0xFFFF); 1255 1255 if (h2 >= 0) 1256 1256 h = (*round)(ACC.qh[i], h2); 1257 1257 else ··· 1260 1260 h = 0xdead; 1261 1261 } 1262 1262 v2 >>= 16; 1263 - result |= ((unsigned64)((unsigned16)h) << s); 1263 + result |= ((uint64_t)((uint16_t)h) << s); 1264 1264 s += 16; 1265 1265 } 1266 1266 return result; 1267 1267 } 1268 1268 1269 - static unsigned64 1270 - qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round) 1269 + static uint64_t 1270 + qh_map_round(sim_cpu *cpu, address_word cia, int16_t h2, QH_ROUND round) 1271 1271 { 1272 - unsigned64 result = 0; 1272 + uint64_t result = 0; 1273 1273 int i, s; 1274 - signed16 h; 1274 + int16_t h; 1275 1275 1276 1276 s = 0; 1277 1277 for (i = 0; i < 4; i++) ··· 1283 1283 UnpredictableResult (); 1284 1284 h = 0xdead; 1285 1285 } 1286 - result |= ((unsigned64)((unsigned16)h) << s); 1286 + result |= ((uint64_t)((uint16_t)h) << s); 1287 1287 s += 16; 1288 1288 } 1289 1289 return result; 1290 1290 } 1291 1291 1292 - static unsigned64 1293 - ob_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, OB_ROUND round) 1292 + static uint64_t 1293 + ob_vector_round(sim_cpu *cpu, address_word cia, uint64_t v2, OB_ROUND round) 1294 1294 { 1295 - unsigned64 result = 0; 1295 + uint64_t result = 0; 1296 1296 int i, s; 1297 - unsigned8 b, b2; 1297 + uint8_t b, b2; 1298 1298 1299 1299 s = 0; 1300 1300 for (i = 0; i < 8; i++) 1301 1301 { 1302 1302 b2 = v2 & 0xFF; v2 >>= 8; 1303 1303 b = (*round)(ACC.ob[i], b2); 1304 - result |= ((unsigned64)b << s); 1304 + result |= ((uint64_t)b << s); 1305 1305 s += 8; 1306 1306 } 1307 1307 return result; 1308 1308 } 1309 1309 1310 - static unsigned64 1311 - ob_map_round(sim_cpu *cpu, address_word cia, unsigned8 b2, OB_ROUND round) 1310 + static uint64_t 1311 + ob_map_round(sim_cpu *cpu, address_word cia, uint8_t b2, OB_ROUND round) 1312 1312 { 1313 - unsigned64 result = 0; 1313 + uint64_t result = 0; 1314 1314 int i, s; 1315 - unsigned8 b; 1315 + uint8_t b; 1316 1316 1317 1317 s = 0; 1318 1318 for (i = 0; i < 8; i++) 1319 1319 { 1320 1320 b = (*round)(ACC.ob[i], b2); 1321 - result |= ((unsigned64)b << s); 1321 + result |= ((uint64_t)b << s); 1322 1322 s += 8; 1323 1323 } 1324 1324 return result; 1325 1325 } 1326 1326 1327 1327 1328 - unsigned64 1328 + uint64_t 1329 1329 mdmx_round_op(sim_cpu *cpu, 1330 1330 address_word cia, 1331 1331 int rm, 1332 1332 int vt, 1333 1333 MX_fmtsel fmtsel) 1334 1334 { 1335 - unsigned64 op2; 1336 - unsigned64 result = 0; 1335 + uint64_t op2; 1336 + uint64_t result = 0; 1337 1337 1338 1338 switch (MX_FMT (fmtsel)) 1339 1339 { ··· 1409 1409 }; 1410 1410 1411 1411 1412 - unsigned64 1412 + uint64_t 1413 1413 mdmx_shuffle(sim_cpu *cpu, 1414 1414 address_word cia, 1415 1415 int shop, 1416 - unsigned64 op1, 1417 - unsigned64 op2) 1416 + uint64_t op1, 1417 + uint64_t op2) 1418 1418 { 1419 - unsigned64 result = 0; 1419 + uint64_t result = 0; 1420 1420 int i, s; 1421 1421 int op; 1422 1422 ··· 1426 1426 s = 0; 1427 1427 for (i = 0; i < 4; i++) 1428 1428 { 1429 - unsigned64 v; 1429 + uint64_t v; 1430 1430 1431 1431 switch (qh_shuffle[op][i].source) 1432 1432 { ··· 1450 1450 s = 0; 1451 1451 for (i = 0; i < 8; i++) 1452 1452 { 1453 - unsigned8 b; 1453 + uint8_t b; 1454 1454 unsigned int ishift = 8*ob_shuffle[op][i].index; 1455 1455 1456 1456 switch (ob_shuffle[op][i].source) ··· 1468 1468 Unpredictable (); 1469 1469 b = 0; 1470 1470 } 1471 - result |= ((unsigned64)b << s); 1471 + result |= ((uint64_t)b << s); 1472 1472 s += 8; 1473 1473 } 1474 1474 }
+2 -2
sim/mips/mdmx.igen
··· 188 188 *mdmx: 189 189 *sb1: 190 190 { 191 - unsigned64 result; 191 + uint64_t result; 192 192 int s; 193 193 check_mdmx (SD_, instruction_0); 194 194 check_mdmx_fmtop (SD_, instruction_0, FMTOP); ··· 205 205 *mdmx: 206 206 *sb1: 207 207 { 208 - unsigned64 result; 208 + uint64_t result; 209 209 int s; 210 210 check_mdmx (SD_, instruction_0); 211 211 check_mdmx_fmtop (SD_, instruction_0, FMTOP);
+2 -2
sim/mips/micromips.igen
··· 81 81 } 82 82 83 83 84 - :function:::unsigned32:compute_movep_src_reg:int reg 84 + :function:::uint32_t:compute_movep_src_reg:int reg 85 85 *micromips32: 86 86 *micromips64: 87 87 { ··· 99 99 } 100 100 } 101 101 102 - :function:::unsigned32:compute_andi16_imm:int encoded_imm 102 + :function:::uint32_t:compute_andi16_imm:int encoded_imm 103 103 *micromips32: 104 104 *micromips64: 105 105 {
+1 -1
sim/mips/micromipsdsp.igen
··· 169 169 "bposge32 <IMMEDIATE>" 170 170 *micromipsdsp: 171 171 { 172 - unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 172 + uint32_t pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK; 173 173 if (pos >= 32) 174 174 NIA = delayslot_micromips (SD_, NIA + (EXTEND12 (IMMEDIATE) << 1), NIA, 175 175 MICROMIPS_DELAYSLOT_SIZE_ANY);
+156 -156
sim/mips/mips.igen
··· 161 161 Programmers Volume III, Revision 0.95, section 4.9. */ 162 162 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) 163 163 == (ksu_user << status_KSU_shift)) 164 - return (address_word)((signed32)base + (signed32)offset); 164 + return (address_word)((int32_t)base + (int32_t)offset); 165 165 #endif 166 166 return base + offset; 167 167 } ··· 263 263 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo 264 264 // to check for restrictions (2) and (3) above. 265 265 // 266 - :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new 266 + :function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new 267 267 { 268 268 if (history->mf.timestamp + 3 > time) 269 269 { ··· 289 289 *vr4100: 290 290 *vr5000: 291 291 { 292 - signed64 time = sim_events_time (SD); 292 + int64_t time = sim_events_time (SD); 293 293 int ok = check_mf_cycles (SD_, history, time, "MT"); 294 294 history->mt.timestamp = time; 295 295 history->mt.cia = CIA; ··· 300 300 *mipsIV: 301 301 *mipsV: 302 302 { 303 - signed64 time = sim_events_time (SD); 303 + int64_t time = sim_events_time (SD); 304 304 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) 305 305 || check_mf_cycles (SD_, history, time, "MT")); 306 306 history->mt.timestamp = time; ··· 317 317 *micromips32: 318 318 *micromips64: 319 319 { 320 - signed64 time = sim_events_time (SD); 320 + int64_t time = sim_events_time (SD); 321 321 history->mt.timestamp = time; 322 322 history->mt.cia = CIA; 323 323 return 1; ··· 345 345 *micromips32: 346 346 *micromips64: 347 347 { 348 - signed64 time = sim_events_time (SD); 348 + int64_t time = sim_events_time (SD); 349 349 int ok = 1; 350 350 if (peer != NULL 351 351 && peer->mt.timestamp > history->op.timestamp ··· 383 383 *vr4100: 384 384 *vr5000: 385 385 { 386 - signed64 time = sim_events_time (SD); 386 + int64_t time = sim_events_time (SD); 387 387 int ok = (check_mf_cycles (SD_, hi, time, "OP") 388 388 && check_mf_cycles (SD_, lo, time, "OP")); 389 389 hi->op.timestamp = time; ··· 397 397 *mipsIV: 398 398 *mipsV: 399 399 { 400 - signed64 time = sim_events_time (SD); 400 + int64_t time = sim_events_time (SD); 401 401 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) 402 402 || (check_mf_cycles (SD_, hi, time, "OP") 403 403 && check_mf_cycles (SD_, lo, time, "OP"))); ··· 418 418 *micromips64: 419 419 { 420 420 /* FIXME: could record the fact that a stall occured if we want */ 421 - signed64 time = sim_events_time (SD); 421 + int64_t time = sim_events_time (SD); 422 422 hi->op.timestamp = time; 423 423 lo->op.timestamp = time; 424 424 hi->op.cia = CIA; ··· 440 440 *vr5000: 441 441 *r3900: 442 442 { 443 - signed64 time = sim_events_time (SD); 443 + int64_t time = sim_events_time (SD); 444 444 int ok = (check_mf_cycles (SD_, hi, time, "OP") 445 445 && check_mf_cycles (SD_, lo, time, "OP")); 446 446 hi->op.timestamp = time; ··· 454 454 *mipsIV: 455 455 *mipsV: 456 456 { 457 - signed64 time = sim_events_time (SD); 457 + int64_t time = sim_events_time (SD); 458 458 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) 459 459 || (check_mf_cycles (SD_, hi, time, "OP") 460 460 && check_mf_cycles (SD_, lo, time, "OP"))); ··· 473 473 *micromips32: 474 474 *micromips64: 475 475 { 476 - signed64 time = sim_events_time (SD); 476 + int64_t time = sim_events_time (SD); 477 477 hi->op.timestamp = time; 478 478 lo->op.timestamp = time; 479 479 hi->op.cia = CIA; ··· 538 538 TRACE_ALU_RESULT (GPR[rd]); 539 539 } 540 540 541 - :function:::void:do_addi:int rs, int rt, unsigned16 immediate 541 + :function:::void:do_addi:int rs, int rt, uint16_t immediate 542 542 { 543 543 if (NotWordValue (GPR[rs])) 544 544 Unpredictable (); ··· 592 592 { 593 593 int s = 32 + shift; 594 594 TRACE_ALU_INPUT2 (GPR[rt], s); 595 - GPR[rd] = ((signed64) GPR[rt]) >> s; 595 + GPR[rd] = ((int64_t) GPR[rt]) >> s; 596 596 TRACE_ALU_RESULT (GPR[rd]); 597 597 } 598 598 ··· 600 600 { 601 601 int s = 32 + shift; 602 602 TRACE_ALU_INPUT2 (GPR[rt], s); 603 - GPR[rd] = (unsigned64) GPR[rt] >> s; 603 + GPR[rd] = (uint64_t) GPR[rt] >> s; 604 604 TRACE_ALU_RESULT (GPR[rd]); 605 605 } 606 606 ··· 655 655 656 656 :function:::void:do_clo:int rd, int rs 657 657 { 658 - unsigned32 temp = GPR[rs]; 659 - unsigned32 i, mask; 658 + uint32_t temp = GPR[rs]; 659 + uint32_t i, mask; 660 660 if (NotWordValue (GPR[rs])) 661 661 Unpredictable (); 662 662 TRACE_ALU_INPUT1 (GPR[rs]); 663 - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) 663 + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) 664 664 { 665 665 if ((temp & mask) == 0) 666 666 break; ··· 672 672 673 673 :function:::void:do_clz:int rd, int rs 674 674 { 675 - unsigned32 temp = GPR[rs]; 676 - unsigned32 i, mask; 675 + uint32_t temp = GPR[rs]; 676 + uint32_t i, mask; 677 677 if (NotWordValue (GPR[rs])) 678 678 Unpredictable (); 679 679 TRACE_ALU_INPUT1 (GPR[rs]); 680 - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) 680 + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) 681 681 { 682 682 if ((temp & mask) != 0) 683 683 break; ··· 689 689 690 690 :function:::void:do_dclo:int rd, int rs 691 691 { 692 - unsigned64 temp = GPR[rs]; 693 - unsigned32 i; 694 - unsigned64 mask; 692 + uint64_t temp = GPR[rs]; 693 + uint32_t i; 694 + uint64_t mask; 695 695 TRACE_ALU_INPUT1 (GPR[rs]); 696 - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) 696 + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) 697 697 { 698 698 if ((temp & mask) == 0) 699 699 break; ··· 705 705 706 706 :function:::void:do_dclz:int rd, int rs 707 707 { 708 - unsigned64 temp = GPR[rs]; 709 - unsigned32 i; 710 - unsigned64 mask; 708 + uint64_t temp = GPR[rs]; 709 + uint32_t i; 710 + uint64_t mask; 711 711 TRACE_ALU_INPUT1 (GPR[rs]); 712 - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) 712 + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) 713 713 { 714 714 if ((temp & mask) != 0) 715 715 break; ··· 791 791 } 792 792 else 793 793 { 794 - unsigned64 memval = 0; 795 - unsigned64 memval1 = 0; 796 - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 794 + uint64_t memval = 0; 795 + uint64_t memval1 = 0; 796 + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 797 797 unsigned int shift = 2; 798 798 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); 799 799 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); ··· 823 823 } 824 824 else 825 825 { 826 - unsigned64 memval = 0; 827 - unsigned64 memval1 = 0; 826 + uint64_t memval = 0; 827 + uint64_t memval1 = 0; 828 828 LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr, 829 829 isDATA, isREAL); 830 830 GPR[rt] = memval; ··· 842 842 843 843 :function:::void:do_madd:int rs, int rt 844 844 { 845 - signed64 temp; 845 + int64_t temp; 846 846 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 847 847 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 848 848 Unpredictable (); 849 849 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 850 850 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 851 - + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); 851 + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 852 852 LO = EXTEND32 (temp); 853 853 HI = EXTEND32 (VH4_8 (temp)); 854 854 TRACE_ALU_RESULT2 (HI, LO); ··· 856 856 857 857 :function:::void:do_dsp_madd:int ac, int rs, int rt 858 858 { 859 - signed64 temp; 859 + int64_t temp; 860 860 if (ac == 0) 861 861 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 862 862 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 863 863 Unpredictable (); 864 864 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 865 865 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 866 - + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); 866 + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 867 867 DSPLO(ac) = EXTEND32 (temp); 868 868 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 869 869 if (ac == 0) ··· 872 872 873 873 :function:::void:do_maddu:int rs, int rt 874 874 { 875 - unsigned64 temp; 875 + uint64_t temp; 876 876 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 877 877 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 878 878 Unpredictable (); 879 879 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 880 880 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 881 - + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); 881 + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 882 882 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 883 883 LO = EXTEND32 (temp); 884 884 HI = EXTEND32 (VH4_8 (temp)); ··· 887 887 888 888 :function:::void:do_dsp_maddu:int ac, int rs, int rt 889 889 { 890 - unsigned64 temp; 890 + uint64_t temp; 891 891 if (ac == 0) 892 892 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 893 893 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 894 894 Unpredictable (); 895 895 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 896 896 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 897 - + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); 897 + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 898 898 if (ac == 0) 899 899 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 900 900 DSPLO(ac) = EXTEND32 (temp); ··· 939 939 940 940 :function:::void:do_msub:int rs, int rt 941 941 { 942 - signed64 temp; 942 + int64_t temp; 943 943 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 944 944 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 945 945 Unpredictable (); 946 946 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 947 947 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 948 - - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); 948 + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 949 949 LO = EXTEND32 (temp); 950 950 HI = EXTEND32 (VH4_8 (temp)); 951 951 TRACE_ALU_RESULT2 (HI, LO); ··· 953 953 954 954 :function:::void:do_dsp_msub:int ac, int rs, int rt 955 955 { 956 - signed64 temp; 956 + int64_t temp; 957 957 if (ac == 0) 958 958 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 959 959 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 960 960 Unpredictable (); 961 961 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 962 962 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 963 - - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs]))); 963 + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 964 964 DSPLO(ac) = EXTEND32 (temp); 965 965 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 966 966 if (ac == 0) ··· 969 969 970 970 :function:::void:do_msubu:int rs, int rt 971 971 { 972 - unsigned64 temp; 972 + uint64_t temp; 973 973 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 974 974 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 975 975 Unpredictable (); 976 976 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 977 977 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 978 - - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); 978 + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 979 979 LO = EXTEND32 (temp); 980 980 HI = EXTEND32 (VH4_8 (temp)); 981 981 TRACE_ALU_RESULT2 (HI, LO); ··· 983 983 984 984 :function:::void:do_dsp_msubu:int ac, int rs, int rt 985 985 { 986 - unsigned64 temp; 986 + uint64_t temp; 987 987 if (ac == 0) 988 988 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 989 989 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 990 990 Unpredictable (); 991 991 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 992 992 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 993 - - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt]))); 993 + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 994 994 DSPLO(ac) = EXTEND32 (temp); 995 995 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 996 996 if (ac == 0) ··· 1025 1025 1026 1026 :function:::void:do_mul:int rd, int rs, int rt 1027 1027 { 1028 - signed64 prod; 1028 + int64_t prod; 1029 1029 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1030 1030 Unpredictable (); 1031 1031 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1032 - prod = (((signed64)(signed32) GPR[rs]) 1033 - * ((signed64)(signed32) GPR[rt])); 1032 + prod = (((int64_t)(int32_t) GPR[rs]) 1033 + * ((int64_t)(int32_t) GPR[rt])); 1034 1034 GPR[rd] = EXTEND32 (VL4_8 (prod)); 1035 1035 TRACE_ALU_RESULT (GPR[rd]); 1036 1036 } 1037 1037 1038 1038 :function:::void:do_dsp_mult:int ac, int rs, int rt 1039 1039 { 1040 - signed64 prod; 1040 + int64_t prod; 1041 1041 if (ac == 0) 1042 1042 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1043 1043 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1044 1044 Unpredictable (); 1045 1045 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1046 - prod = ((signed64)(signed32) GPR[rs]) 1047 - * ((signed64)(signed32) GPR[rt]); 1046 + prod = ((int64_t)(int32_t) GPR[rs]) 1047 + * ((int64_t)(int32_t) GPR[rt]); 1048 1048 DSPLO(ac) = EXTEND32 (VL4_8 (prod)); 1049 1049 DSPHI(ac) = EXTEND32 (VH4_8 (prod)); 1050 1050 if (ac == 0) ··· 1056 1056 1057 1057 :function:::void:do_dsp_multu:int ac, int rs, int rt 1058 1058 { 1059 - unsigned64 prod; 1059 + uint64_t prod; 1060 1060 if (ac == 0) 1061 1061 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1062 1062 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1063 1063 Unpredictable (); 1064 1064 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1065 - prod = ((unsigned64)(unsigned32) GPR[rs]) 1066 - * ((unsigned64)(unsigned32) GPR[rt]); 1065 + prod = ((uint64_t)(uint32_t) GPR[rs]) 1066 + * ((uint64_t)(uint32_t) GPR[rt]); 1067 1067 DSPLO(ac) = EXTEND32 (VL4_8 (prod)); 1068 1068 DSPHI(ac) = EXTEND32 (VH4_8 (prod)); 1069 1069 if (ac == 0) ··· 1083 1083 1084 1084 :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0 1085 1085 { 1086 - unsigned32 instruction = instruction_0; 1086 + uint32_t instruction = instruction_0; 1087 1087 address_word base = GPR[basereg]; 1088 1088 address_word offset = EXTEND16 (offsetarg); 1089 1089 { ··· 1097 1097 } 1098 1098 else 1099 1099 { 1100 - unsigned64 memval = 0; 1101 - unsigned64 memval1 = 0; 1102 - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1100 + uint64_t memval = 0; 1101 + uint64_t memval1 = 0; 1102 + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1103 1103 address_word reverseendian = 1104 1104 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 1105 1105 address_word bigendiancpu = ··· 1107 1107 unsigned int byte; 1108 1108 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 1109 1109 byte = ((vaddr & mask) ^ bigendiancpu); 1110 - memval = ((unsigned64) GPR[rt] << (8 * byte)); 1110 + memval = ((uint64_t) GPR[rt] << (8 * byte)); 1111 1111 if (LLBIT) 1112 1112 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, 1113 1113 isREAL); ··· 1131 1131 } 1132 1132 else 1133 1133 { 1134 - unsigned64 memval = 0; 1135 - unsigned64 memval1 = 0; 1134 + uint64_t memval = 0; 1135 + uint64_t memval1 = 0; 1136 1136 memval = GPR[rt]; 1137 1137 if (LLBIT) 1138 1138 StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, ··· 1248 1248 1249 1249 :function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0 1250 1250 { 1251 - unsigned64 fsx; 1252 - unsigned64 ftx; 1253 - unsigned64 fdx; 1251 + uint64_t fsx; 1252 + uint64_t ftx; 1253 + uint64_t fdx; 1254 1254 check_fpu (SD_); 1255 1255 check_u64 (SD_, instruction_0); 1256 1256 fsx = ValueFPR (fs, fmt_ps); ··· 1493 1493 } 1494 1494 else 1495 1495 { 1496 - unsigned64 fdx; 1496 + uint64_t fdx; 1497 1497 fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd, 1498 1498 fmt_ps)), 1499 1499 PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd, ··· 1730 1730 } 1731 1731 else 1732 1732 { 1733 - unsigned64 memval = 0; 1734 - unsigned64 memval1 = 0; 1735 - unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1733 + uint64_t memval = 0; 1734 + uint64_t memval1 = 0; 1735 + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1736 1736 address_word reverseendian = 1737 1737 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 1738 1738 address_word bigendiancpu = ··· 1740 1740 unsigned int byte; 1741 1741 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 1742 1742 byte = ((vaddr & mask) ^ bigendiancpu); 1743 - memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); 1743 + memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte)); 1744 1744 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, 1745 1745 isREAL); 1746 1746 } ··· 1794 1794 1795 1795 1796 1796 1797 - :function:::void:do_addiu:int rs, int rt, unsigned16 immediate 1797 + :function:::void:do_addiu:int rs, int rt, uint16_t immediate 1798 1798 { 1799 1799 if (NotWordValue (GPR[rs])) 1800 1800 Unpredictable (); ··· 2395 2395 2396 2396 2397 2397 2398 - :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate 2398 + :function:::void:do_daddiu:int rs, int rt, uint16_t immediate 2399 2399 { 2400 2400 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 2401 2401 GPR[rt] = GPR[rs] + EXTEND16 (immediate); ··· 2474 2474 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2475 2475 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2476 2476 { 2477 - signed64 n = GPR[rs]; 2478 - signed64 d = GPR[rt]; 2479 - signed64 hi; 2480 - signed64 lo; 2477 + int64_t n = GPR[rs]; 2478 + int64_t d = GPR[rt]; 2479 + int64_t hi; 2480 + int64_t lo; 2481 2481 if (d == 0) 2482 2482 { 2483 2483 lo = SIGNED64 (0x8000000000000000); ··· 2520 2520 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2521 2521 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2522 2522 { 2523 - unsigned64 n = GPR[rs]; 2524 - unsigned64 d = GPR[rt]; 2525 - unsigned64 hi; 2526 - unsigned64 lo; 2523 + uint64_t n = GPR[rs]; 2524 + uint64_t d = GPR[rt]; 2525 + uint64_t hi; 2526 + uint64_t lo; 2527 2527 if (d == 0) 2528 2528 { 2529 2529 lo = SIGNED64 (0x8000000000000000); ··· 2559 2559 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2560 2560 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2561 2561 { 2562 - signed32 n = GPR[rs]; 2563 - signed32 d = GPR[rt]; 2562 + int32_t n = GPR[rs]; 2563 + int32_t d = GPR[rt]; 2564 2564 if (d == 0) 2565 2565 { 2566 2566 LO = EXTEND32 (0x80000000); ··· 2605 2605 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2606 2606 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2607 2607 { 2608 - unsigned32 n = GPR[rs]; 2609 - unsigned32 d = GPR[rt]; 2608 + uint32_t n = GPR[rs]; 2609 + uint32_t d = GPR[rt]; 2610 2610 if (d == 0) 2611 2611 { 2612 2612 LO = EXTEND32 (0x80000000); ··· 2642 2642 2643 2643 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p 2644 2644 { 2645 - unsigned64 lo; 2646 - unsigned64 hi; 2647 - unsigned64 m00; 2648 - unsigned64 m01; 2649 - unsigned64 m10; 2650 - unsigned64 m11; 2651 - unsigned64 mid; 2645 + uint64_t lo; 2646 + uint64_t hi; 2647 + uint64_t m00; 2648 + uint64_t m01; 2649 + uint64_t m10; 2650 + uint64_t m11; 2651 + uint64_t mid; 2652 2652 int sign; 2653 - unsigned64 op1 = GPR[rs]; 2654 - unsigned64 op2 = GPR[rt]; 2653 + uint64_t op1 = GPR[rs]; 2654 + uint64_t op2 = GPR[rt]; 2655 2655 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2656 2656 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2657 2657 /* make signed multiply unsigned */ 2658 2658 sign = 0; 2659 2659 if (signed_p) 2660 2660 { 2661 - if ((signed64) op1 < 0) 2661 + if ((int64_t) op1 < 0) 2662 2662 { 2663 2663 op1 = - op1; 2664 2664 ++sign; 2665 2665 } 2666 - if ((signed64) op2 < 0) 2666 + if ((int64_t) op2 < 0) 2667 2667 { 2668 2668 op2 = - op2; 2669 2669 ++sign; 2670 2670 } 2671 2671 } 2672 2672 /* multiply out the 4 sub products */ 2673 - m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); 2674 - m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); 2675 - m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); 2676 - m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); 2673 + m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2)); 2674 + m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2)); 2675 + m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2)); 2676 + m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2)); 2677 2677 /* add the products */ 2678 - mid = ((unsigned64) VH4_8 (m00) 2679 - + (unsigned64) VL4_8 (m10) 2680 - + (unsigned64) VL4_8 (m01)); 2678 + mid = ((uint64_t) VH4_8 (m00) 2679 + + (uint64_t) VL4_8 (m10) 2680 + + (uint64_t) VL4_8 (m01)); 2681 2681 lo = U8_4 (mid, m00); 2682 2682 hi = (m11 2683 - + (unsigned64) VH4_8 (mid) 2684 - + (unsigned64) VH4_8 (m01) 2685 - + (unsigned64) VH4_8 (m10)); 2683 + + (uint64_t) VH4_8 (mid) 2684 + + (uint64_t) VH4_8 (m01) 2685 + + (uint64_t) VH4_8 (m10)); 2686 2686 /* fix the sign */ 2687 2687 if (sign & 1) 2688 2688 { ··· 2757 2757 } 2758 2758 2759 2759 2760 - :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y 2760 + :function:::uint64_t:do_dror:uint64_t x,uint64_t y 2761 2761 { 2762 - unsigned64 result; 2762 + uint64_t result; 2763 2763 2764 2764 y &= 63; 2765 2765 TRACE_ALU_INPUT2 (x, y); ··· 2860 2860 :function:::void:do_dsra:int rt, int rd, int shift 2861 2861 { 2862 2862 TRACE_ALU_INPUT2 (GPR[rt], shift); 2863 - GPR[rd] = ((signed64) GPR[rt]) >> shift; 2863 + GPR[rd] = ((int64_t) GPR[rt]) >> shift; 2864 2864 TRACE_ALU_RESULT (GPR[rd]); 2865 2865 } 2866 2866 ··· 2899 2899 { 2900 2900 int s = MASKED64 (GPR[rs], 5, 0); 2901 2901 TRACE_ALU_INPUT2 (GPR[rt], s); 2902 - GPR[rd] = ((signed64) GPR[rt]) >> s; 2902 + GPR[rd] = ((int64_t) GPR[rt]) >> s; 2903 2903 TRACE_ALU_RESULT (GPR[rd]); 2904 2904 } 2905 2905 ··· 2920 2920 :function:::void:do_dsrl:int rt, int rd, int shift 2921 2921 { 2922 2922 TRACE_ALU_INPUT2 (GPR[rt], shift); 2923 - GPR[rd] = (unsigned64) GPR[rt] >> shift; 2923 + GPR[rd] = (uint64_t) GPR[rt] >> shift; 2924 2924 TRACE_ALU_RESULT (GPR[rd]); 2925 2925 } 2926 2926 ··· 2959 2959 { 2960 2960 int s = MASKED64 (GPR[rs], 5, 0); 2961 2961 TRACE_ALU_INPUT2 (GPR[rt], s); 2962 - GPR[rd] = (unsigned64) GPR[rt] >> s; 2962 + GPR[rd] = (uint64_t) GPR[rt] >> s; 2963 2963 TRACE_ALU_RESULT (GPR[rd]); 2964 2964 } 2965 2965 ··· 3126 3126 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 3127 3127 unsigned int byte; 3128 3128 address_word paddr; 3129 - unsigned64 memval; 3129 + uint64_t memval; 3130 3130 address_word vaddr; 3131 3131 3132 3132 paddr = vaddr = loadstore_ea (SD_, base, offset); ··· 3148 3148 unsigned int byte; 3149 3149 unsigned int word; 3150 3150 address_word paddr; 3151 - unsigned64 memval; 3151 + uint64_t memval; 3152 3152 address_word vaddr; 3153 3153 int nr_lhs_bits; 3154 3154 int nr_rhs_bits; ··· 3168 3168 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 3169 3169 3170 3170 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 3171 - (long) ((unsigned64) vaddr >> 32), (long) vaddr, 3172 - (long) ((unsigned64) paddr >> 32), (long) paddr, 3171 + (long) ((uint64_t) vaddr >> 32), (long) vaddr, 3172 + (long) ((uint64_t) paddr >> 32), (long) paddr, 3173 3173 word, byte, nr_lhs_bits, nr_rhs_bits); */ 3174 3174 3175 3175 LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL); ··· 3187 3187 rt = (rt & ~lhs_mask) | (temp & lhs_mask); 3188 3188 3189 3189 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", 3190 - (long) ((unsigned64) memval >> 32), (long) memval, 3191 - (long) ((unsigned64) temp >> 32), (long) temp, 3192 - (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, 3190 + (long) ((uint64_t) memval >> 32), (long) memval, 3191 + (long) ((uint64_t) temp >> 32), (long) temp, 3192 + (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask, 3193 3193 (long) (rt >> 32), (long) rt); */ 3194 3194 return rt; 3195 3195 } ··· 3201 3201 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 3202 3202 unsigned int byte; 3203 3203 address_word paddr; 3204 - unsigned64 memval; 3204 + uint64_t memval; 3205 3205 address_word vaddr; 3206 3206 3207 3207 paddr = vaddr = loadstore_ea (SD_, base, offset); ··· 3763 3763 3764 3764 :function:::void:do_mult:int rs, int rt, int rd 3765 3765 { 3766 - signed64 prod; 3766 + int64_t prod; 3767 3767 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 3768 3768 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 3769 3769 Unpredictable (); 3770 3770 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3771 - prod = (((signed64)(signed32) GPR[rs]) 3772 - * ((signed64)(signed32) GPR[rt])); 3771 + prod = (((int64_t)(int32_t) GPR[rs]) 3772 + * ((int64_t)(int32_t) GPR[rt])); 3773 3773 LO = EXTEND32 (VL4_8 (prod)); 3774 3774 HI = EXTEND32 (VH4_8 (prod)); 3775 3775 ACX = 0; /* SmartMIPS */ ··· 3816 3816 3817 3817 :function:::void:do_multu:int rs, int rt, int rd 3818 3818 { 3819 - unsigned64 prod; 3819 + uint64_t prod; 3820 3820 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 3821 3821 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 3822 3822 Unpredictable (); 3823 3823 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3824 - prod = (((unsigned64)(unsigned32) GPR[rs]) 3825 - * ((unsigned64)(unsigned32) GPR[rt])); 3824 + prod = (((uint64_t)(uint32_t) GPR[rs]) 3825 + * ((uint64_t)(uint32_t) GPR[rt])); 3826 3826 LO = EXTEND32 (VL4_8 (prod)); 3827 3827 HI = EXTEND32 (VH4_8 (prod)); 3828 3828 if (rd != 0) ··· 3959 3959 } 3960 3960 3961 3961 3962 - :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y 3962 + :function:::uint64_t:do_ror:uint32_t x,uint32_t y 3963 3963 { 3964 - unsigned64 result; 3964 + uint64_t result; 3965 3965 3966 3966 y &= 31; 3967 3967 TRACE_ALU_INPUT2 (x, y); ··· 4000 4000 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 4001 4001 unsigned int byte; 4002 4002 address_word paddr; 4003 - unsigned64 memval; 4003 + uint64_t memval; 4004 4004 address_word vaddr; 4005 4005 4006 4006 paddr = vaddr = loadstore_ea (SD_, base, offset); ··· 4022 4022 unsigned int byte; 4023 4023 unsigned int word; 4024 4024 address_word paddr; 4025 - unsigned64 memval; 4025 + uint64_t memval; 4026 4026 address_word vaddr; 4027 4027 int nr_lhs_bits; 4028 4028 int nr_rhs_bits; ··· 4039 4039 nr_rhs_bits = 8 * access - 8 * byte; 4040 4040 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 4041 4041 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 4042 - (long) ((unsigned64) vaddr >> 32), (long) vaddr, 4043 - (long) ((unsigned64) paddr >> 32), (long) paddr, 4042 + (long) ((uint64_t) vaddr >> 32), (long) vaddr, 4043 + (long) ((uint64_t) paddr >> 32), (long) paddr, 4044 4044 word, byte, nr_lhs_bits, nr_rhs_bits); */ 4045 4045 4046 4046 if (word == 0) ··· 4052 4052 memval = (rt << nr_lhs_bits); 4053 4053 } 4054 4054 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", 4055 - (long) ((unsigned64) rt >> 32), (long) rt, 4056 - (long) ((unsigned64) memval >> 32), (long) memval); */ 4055 + (long) ((uint64_t) rt >> 32), (long) rt, 4056 + (long) ((uint64_t) memval >> 32), (long) memval); */ 4057 4057 StoreMemory (byte, memval, 0, paddr, vaddr, isREAL); 4058 4058 } 4059 4059 ··· 4064 4064 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 4065 4065 unsigned int byte; 4066 4066 address_word paddr; 4067 - unsigned64 memval; 4067 + uint64_t memval; 4068 4068 address_word vaddr; 4069 4069 4070 4070 paddr = vaddr = loadstore_ea (SD_, base, offset); ··· 4212 4212 4213 4213 :function:::void:do_sll:int rt, int rd, int shift 4214 4214 { 4215 - unsigned32 temp = (GPR[rt] << shift); 4215 + uint32_t temp = (GPR[rt] << shift); 4216 4216 TRACE_ALU_INPUT2 (GPR[rt], shift); 4217 4217 GPR[rd] = EXTEND32 (temp); 4218 4218 TRACE_ALU_RESULT (GPR[rd]); ··· 4255 4255 :function:::void:do_sllv:int rs, int rt, int rd 4256 4256 { 4257 4257 int s = MASKED (GPR[rs], 4, 0); 4258 - unsigned32 temp = (GPR[rt] << s); 4258 + uint32_t temp = (GPR[rt] << s); 4259 4259 TRACE_ALU_INPUT2 (GPR[rt], s); 4260 4260 GPR[rd] = EXTEND32 (temp); 4261 4261 TRACE_ALU_RESULT (GPR[rd]); ··· 4306 4306 } 4307 4307 4308 4308 4309 - :function:::void:do_slti:int rs, int rt, unsigned16 immediate 4309 + :function:::void:do_slti:int rs, int rt, uint16_t immediate 4310 4310 { 4311 4311 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 4312 4312 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); ··· 4332 4332 } 4333 4333 4334 4334 4335 - :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate 4335 + :function:::void:do_sltiu:int rs, int rt, uint16_t immediate 4336 4336 { 4337 4337 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 4338 4338 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); ··· 4387 4387 4388 4388 :function:::void:do_sra:int rt, int rd, int shift 4389 4389 { 4390 - signed32 temp = (signed32) GPR[rt] >> shift; 4390 + int32_t temp = (int32_t) GPR[rt] >> shift; 4391 4391 if (NotWordValue (GPR[rt])) 4392 4392 Unpredictable (); 4393 4393 TRACE_ALU_INPUT2 (GPR[rt], shift); ··· 4418 4418 :function:::void:do_srav:int rs, int rt, int rd 4419 4419 { 4420 4420 int s = MASKED (GPR[rs], 4, 0); 4421 - signed32 temp = (signed32) GPR[rt] >> s; 4421 + int32_t temp = (int32_t) GPR[rt] >> s; 4422 4422 if (NotWordValue (GPR[rt])) 4423 4423 Unpredictable (); 4424 4424 TRACE_ALU_INPUT2 (GPR[rt], s); ··· 4448 4448 4449 4449 :function:::void:do_srl:int rt, int rd, int shift 4450 4450 { 4451 - unsigned32 temp = (unsigned32) GPR[rt] >> shift; 4451 + uint32_t temp = (uint32_t) GPR[rt] >> shift; 4452 4452 if (NotWordValue (GPR[rt])) 4453 4453 Unpredictable (); 4454 4454 TRACE_ALU_INPUT2 (GPR[rt], shift); ··· 4478 4478 :function:::void:do_srlv:int rs, int rt, int rd 4479 4479 { 4480 4480 int s = MASKED (GPR[rs], 4, 0); 4481 - unsigned32 temp = (unsigned32) GPR[rt] >> s; 4481 + uint32_t temp = (uint32_t) GPR[rt] >> s; 4482 4482 if (NotWordValue (GPR[rt])) 4483 4483 Unpredictable (); 4484 4484 TRACE_ALU_INPUT2 (GPR[rt], s); ··· 4896 4896 } 4897 4897 4898 4898 4899 - :function:::void:do_xori:int rs, int rt, unsigned16 immediate 4899 + :function:::void:do_xori:int rs, int rt, uint16_t immediate 4900 4900 { 4901 4901 TRACE_ALU_INPUT2 (GPR[rs], immediate); 4902 4902 GPR[rt] = GPR[rs] ^ immediate; ··· 5060 5060 // unsigned_word, which is limited to the size of the machine's registers. 5061 5061 // 5062 5062 5063 - :function:::unsigned64:do_load_double:address_word base, address_word offset 5063 + :function:::uint64_t:do_load_double:address_word base, address_word offset 5064 5064 *mipsII: 5065 5065 *mips32: 5066 5066 *mips32r2: ··· 5069 5069 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 5070 5070 address_word vaddr; 5071 5071 address_word paddr; 5072 - unsigned64 memval; 5073 - unsigned64 v; 5072 + uint64_t memval; 5073 + uint64_t v; 5074 5074 5075 5075 paddr = vaddr = loadstore_ea (SD_, base, offset); 5076 5076 if ((vaddr & AccessLength_DOUBLEWORD) != 0) ··· 5080 5080 sim_core_unaligned_signal); 5081 5081 } 5082 5082 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL); 5083 - v = (unsigned64)memval; 5083 + v = (uint64_t)memval; 5084 5084 LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA, 5085 5085 isREAL); 5086 5086 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); ··· 5094 5094 // unsigned_word, which is limited to the size of the machine's registers. 5095 5095 // 5096 5096 5097 - :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v 5097 + :function:::void:do_store_double:address_word base, address_word offset, uint64_t v 5098 5098 *mipsII: 5099 5099 *mips32: 5100 5100 *mips32r2: ··· 5103 5103 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 5104 5104 address_word vaddr; 5105 5105 address_word paddr; 5106 - unsigned64 memval; 5106 + uint64_t memval; 5107 5107 5108 5108 paddr = vaddr = loadstore_ea (SD_, base, offset); 5109 5109 if ((vaddr & AccessLength_DOUBLEWORD) != 0) ··· 5504 5504 "dmfc1 r<RT>, f<FS>" 5505 5505 *mipsIII: 5506 5506 { 5507 - unsigned64 v; 5507 + uint64_t v; 5508 5508 check_fpu (SD_); 5509 5509 check_u64 (SD_, instruction_0); 5510 5510 if (SizeFGR () == 64) ··· 5537 5537 "dmtc1 r<RT>, f<FS>" 5538 5538 *mipsIII: 5539 5539 { 5540 - unsigned64 v; 5540 + uint64_t v; 5541 5541 check_fpu (SD_); 5542 5542 check_u64 (SD_, instruction_0); 5543 5543 if (SizeFGR () == 64) ··· 5724 5724 *mipsII: 5725 5725 *mipsIII: 5726 5726 { 5727 - unsigned64 v; 5727 + uint64_t v; 5728 5728 check_fpu (SD_); 5729 5729 v = EXTEND32 (FGR[FS]); 5730 5730 PENDING_FILL (RT, v);
+3 -3
sim/mips/mips3264r2.igen
··· 21 21 22 22 :function:::void:do_dsbh:int rd, int rt 23 23 { 24 - union { unsigned64 d; unsigned16 h[4]; } u; 24 + union { uint64_t d; uint16_t h[4]; } u; 25 25 TRACE_ALU_INPUT1 (GPR[rt]); 26 26 u.d = GPR[rt]; 27 27 u.h[0] = SWAP_2 (u.h[0]); ··· 34 34 35 35 :function:::void:do_dshd:int rd, int rt 36 36 { 37 - unsigned64 d; 37 + uint64_t d; 38 38 TRACE_ALU_INPUT1 (GPR[rt]); 39 39 d = GPR[rt]; 40 40 GPR[rd] = ((d >> 48) ··· 181 181 182 182 :function:::void:do_wsbh:int rd, int rt 183 183 { 184 - union { unsigned32 w; unsigned16 h[2]; } u; 184 + union { uint32_t w; uint16_t h[2]; } u; 185 185 TRACE_ALU_INPUT1 (GPR[rt]); 186 186 u.w = GPR[rt]; 187 187 u.h[0] = SWAP_2 (u.h[0]);
+10 -10
sim/mips/sim-main.c
··· 254 254 } 255 255 256 256 257 - INLINE_SIM_MAIN (unsigned32) 257 + INLINE_SIM_MAIN (uint32_t) 258 258 ifetch32 (SIM_DESC SD, 259 259 sim_cpu *CPU, 260 260 address_word cia, ··· 267 267 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 268 268 unsigned int byte; 269 269 address_word paddr = vaddr; 270 - unsigned64 memval; 270 + uint64_t memval; 271 271 272 272 if ((vaddr & access) != 0) 273 273 SignalExceptionInstructionFetch (); ··· 278 278 } 279 279 280 280 281 - INLINE_SIM_MAIN (unsigned16) 281 + INLINE_SIM_MAIN (uint16_t) 282 282 ifetch16 (SIM_DESC SD, 283 283 sim_cpu *CPU, 284 284 address_word cia, ··· 291 291 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 292 292 unsigned int byte; 293 293 address_word paddr = vaddr; 294 - unsigned64 memval; 294 + uint64_t memval; 295 295 296 296 if ((vaddr & access) != 0) 297 297 SignalExceptionInstructionFetch (); ··· 433 433 { 434 434 case 4: 435 435 if (PENDING_SLOT_VALUE[index]) 436 - *(unsigned32*)PENDING_SLOT_DEST[index] |= 436 + *(uint32_t*)PENDING_SLOT_DEST[index] |= 437 437 BIT32 (PENDING_SLOT_BIT[index]); 438 438 else 439 - *(unsigned32*)PENDING_SLOT_DEST[index] &= 439 + *(uint32_t*)PENDING_SLOT_DEST[index] &= 440 440 BIT32 (PENDING_SLOT_BIT[index]); 441 441 break; 442 442 case 8: 443 443 if (PENDING_SLOT_VALUE[index]) 444 - *(unsigned64*)PENDING_SLOT_DEST[index] |= 444 + *(uint64_t*)PENDING_SLOT_DEST[index] |= 445 445 BIT64 (PENDING_SLOT_BIT[index]); 446 446 else 447 - *(unsigned64*)PENDING_SLOT_DEST[index] &= 447 + *(uint64_t*)PENDING_SLOT_DEST[index] &= 448 448 BIT64 (PENDING_SLOT_BIT[index]); 449 449 break; 450 450 } ··· 452 452 switch (PENDING_SLOT_SIZE[index]) 453 453 { 454 454 case 4: 455 - *(unsigned32*)PENDING_SLOT_DEST[index] = 455 + *(uint32_t*)PENDING_SLOT_DEST[index] = 456 456 PENDING_SLOT_VALUE[index]; 457 457 break; 458 458 case 8: 459 - *(unsigned64*)PENDING_SLOT_DEST[index] = 459 + *(uint64_t*)PENDING_SLOT_DEST[index] = 460 460 PENDING_SLOT_VALUE[index]; 461 461 break; 462 462 }
+49 -49
sim/mips/sim-main.h
··· 33 33 /* Deprecated macros and types for manipulating 64bit values. Use 34 34 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ 35 35 36 - typedef signed64 word64; 37 - typedef unsigned64 uword64; 36 + typedef int64_t word64; 37 + typedef uint64_t uword64; 38 38 39 39 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) 40 40 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) ··· 115 115 more details. */ 116 116 117 117 typedef struct _hilo_access { 118 - signed64 timestamp; 118 + int64_t timestamp; 119 119 address_word cia; 120 120 } hilo_access; 121 121 ··· 135 135 #define ALU32_END(ANS) \ 136 136 if (ALU32_HAD_OVERFLOW) \ 137 137 SignalExceptionIntegerOverflow (); \ 138 - (ANS) = (signed32) ALU32_OVERFLOW_RESULT 138 + (ANS) = (int32_t) ALU32_OVERFLOW_RESULT 139 139 140 140 141 141 #define ALU64_END(ANS) \ ··· 163 163 int slot_size[PSLOTS]; 164 164 int slot_bit[PSLOTS]; 165 165 void *slot_dest[PSLOTS]; 166 - unsigned64 slot_value[PSLOTS]; 166 + uint64_t slot_value[PSLOTS]; 167 167 } pending_write_queue; 168 168 169 169 #ifndef PENDING_TRACE ··· 243 243 32 or 64 bits. Since the accumulators are 2's complement with 244 244 overflow suppressed, high-order bits can be ignored in most contexts. */ 245 245 246 - typedef signed32 signed24; 247 - typedef signed64 signed48; 246 + typedef int32_t signed24; 247 + typedef int64_t signed48; 248 248 249 249 typedef union { 250 250 signed24 ob[8]; ··· 700 700 701 701 702 702 /* FPR access. */ 703 - unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); 703 + uint64_t value_fpr (SIM_STATE, int fpr, FP_formats); 704 704 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) 705 - void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); 705 + void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value); 706 706 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) 707 - unsigned64 ps_lower (SIM_STATE, unsigned64 op); 707 + uint64_t ps_lower (SIM_STATE, uint64_t op); 708 708 #define PSLower(op) ps_lower (SIM_ARGS, op) 709 - unsigned64 ps_upper (SIM_STATE, unsigned64 op); 709 + uint64_t ps_upper (SIM_STATE, uint64_t op); 710 710 #define PSUpper(op) ps_upper (SIM_ARGS, op) 711 - unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); 711 + uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from); 712 712 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) 713 713 714 714 ··· 722 722 723 723 724 724 /* FPU operations. */ 725 - void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); 725 + void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, int abs, int cond, int cc); 726 726 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) 727 - unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); 727 + uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt); 728 728 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) 729 - unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); 729 + uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt); 730 730 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) 731 - unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 731 + uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 732 732 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) 733 - unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 733 + uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 734 734 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) 735 - unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 735 + uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 736 736 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) 737 - unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 737 + uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 738 738 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) 739 - unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); 739 + uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt); 740 740 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) 741 - unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 741 + uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt); 742 742 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) 743 - unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); 743 + uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt); 744 744 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) 745 - unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, 746 - unsigned64 op3, FP_formats fmt); 745 + uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2, 746 + uint64_t op3, FP_formats fmt); 747 747 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) 748 - unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, 749 - unsigned64 op3, FP_formats fmt); 748 + uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2, 749 + uint64_t op3, FP_formats fmt); 750 750 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) 751 - unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, 752 - unsigned64 op3, FP_formats fmt); 751 + uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2, 752 + uint64_t op3, FP_formats fmt); 753 753 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) 754 - unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, 755 - unsigned64 op3, FP_formats fmt); 754 + uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2, 755 + uint64_t op3, FP_formats fmt); 756 756 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) 757 - unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); 757 + uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to); 758 758 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) 759 - unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, 759 + uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from, 760 760 FP_formats to); 761 761 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) 762 762 ··· 764 764 /* MIPS-3D ASE operations. */ 765 765 #define CompareAbs(op1,op2,fmt,cond,cc) \ 766 766 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) 767 - unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 767 + uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 768 768 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) 769 - unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 769 + uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 770 770 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) 771 - unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); 771 + uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt); 772 772 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) 773 - unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 773 + uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 774 774 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) 775 - unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); 775 + uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt); 776 776 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) 777 - unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); 777 + uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 778 778 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) 779 779 780 780 ··· 802 802 #define MX_VECT_ABSD (13) /* SB-1 only. */ 803 803 #define MX_VECT_AVG (14) /* SB-1 only. */ 804 804 805 - unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 805 + uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 806 806 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) 807 807 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) 808 808 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) ··· 822 822 #define MX_C_EQ 0x1 823 823 #define MX_C_LT 0x4 824 824 825 - void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); 825 + void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel); 826 826 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) 827 827 828 - unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); 828 + uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel); 829 829 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) 830 830 831 831 #define MX_VECT_ADDA (0) ··· 838 838 #define MX_VECT_SUBL (7) 839 839 #define MX_VECT_ABSDA (8) /* SB-1 only. */ 840 840 841 - void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); 841 + void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 842 842 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) 843 843 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) 844 844 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) ··· 857 857 #define MX_RAC_M (1) 858 858 #define MX_RAC_H (2) 859 859 860 - unsigned64 mdmx_rac_op (SIM_STATE, int, int); 860 + uint64_t mdmx_rac_op (SIM_STATE, int, int); 861 861 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) 862 862 863 - void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); 863 + void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t); 864 864 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) 865 - void mdmx_wach (SIM_STATE, int, unsigned64); 865 + void mdmx_wach (SIM_STATE, int, uint64_t); 866 866 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) 867 867 868 868 #define MX_RND_AS (0) ··· 872 872 #define MX_RND_ZS (4) 873 873 #define MX_RND_ZU (5) 874 874 875 - unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 875 + uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 876 876 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) 877 877 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) 878 878 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) ··· 880 880 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) 881 881 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) 882 882 883 - unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); 883 + uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t); 884 884 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) 885 885 886 886 ··· 937 937 #define Unpredictable() unpredictable (SD_) 938 938 #define UnpredictableResult() /* For now, do nothing. */ 939 939 940 - INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 940 + INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 941 941 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) 942 - INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 942 + INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 943 943 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) 944 944 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) 945 945 #define IMEM32_MICROMIPS(CIA) \
+4 -4
sim/mips/smartmips.igen
··· 31 31 "maddp r<RS>, r<RT>" 32 32 *smartmips: 33 33 { 34 - unsigned64 res; 35 - unsigned64 rs, rt; 34 + uint64_t res; 35 + uint64_t rs, rt; 36 36 int i; 37 37 38 38 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); ··· 83 83 "multp r<RS>, r<RT>" 84 84 *smartmips: 85 85 { 86 - unsigned64 res; 87 - unsigned64 rs, rt; 86 + uint64_t res; 87 + uint64_t rs, rt; 88 88 int i; 89 89 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 90 90 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+6 -6
sim/mips/tx.igen
··· 8 8 "madd r<RD>, r<RS>, r<RT>" 9 9 *r3900 10 10 { 11 - signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 12 - + ((signed64) EXTEND32 (GPR[RT]) 13 - * (signed64) EXTEND32 (GPR[RS]))); 11 + int64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 12 + + ((int64_t) EXTEND32 (GPR[RT]) 13 + * (int64_t) EXTEND32 (GPR[RS]))); 14 14 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 15 15 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 16 16 LO = EXTEND32 (prod); ··· 26 26 "maddu r<RD>, r<RS>, r<RT>" 27 27 *r3900 28 28 { 29 - unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 30 - + ((unsigned64) VL4_8 (GPR[RS]) 31 - * (unsigned64) VL4_8 (GPR[RT]))); 29 + uint64_t prod = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 30 + + ((uint64_t) VL4_8 (GPR[RS]) 31 + * (uint64_t) VL4_8 (GPR[RT]))); 32 32 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 33 33 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); 34 34 LO = EXTEND32 (prod);
+4 -4
sim/mips/vr.igen
··· 40 40 // concatenation of the low 32 bits of HI and LO. 41 41 :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p 42 42 { 43 - unsigned64 lhs, x, y, xcut, ycut, product, result; 43 + uint64_t lhs, x, y, xcut, ycut, product, result; 44 44 45 45 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 46 46 ··· 82 82 /* Saturate the result to 32 bits. An unsigned, unsaturated 83 83 result is zero-extended to 64 bits, but unsigned overflow 84 84 causes all 64 bits to be set. */ 85 - if (!unsigned_p && (unsigned64) EXTEND32 (result) != result) 86 - result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff); 85 + if (!unsigned_p && (uint64_t) EXTEND32 (result) != result) 86 + result = ((int64_t) result < 0 ? -0x7fffffff - 1 : 0x7fffffff); 87 87 else if (unsigned_p && (result >> 32) != 0) 88 - result = (unsigned64) 0 - 1; 88 + result = (uint64_t) 0 - 1; 89 89 } 90 90 TRACE_ALU_RESULT (result); 91 91