-2

gas/config/tc-aarch64.c

Reviewed

··· 6460 6460 case AARCH64_OPND_Em: 6461 6461 case AARCH64_OPND_Em16: 6462 6462 case AARCH64_OPND_Em8: 6463 6463 - case AARCH64_OPND_SM3_IMM2: 6464 6463 operand->reglane.regno = default_value; 6465 6464 break; 6466 6465 ··· 7050 7049 case AARCH64_OPND_Em: 7051 7050 case AARCH64_OPND_Em16: 7052 7051 case AARCH64_OPND_Em8: 7053 7053 - case AARCH64_OPND_SM3_IMM2: 7054 7052 reg_type = REG_TYPE_V; 7055 7053 vector_reg_index: 7056 7054 reg = aarch64_reg_parse (&str, reg_type, &vectype);

-1

include/opcode/aarch64.h

Reviewed

··· 987 987 AARCH64_OPND_SME_ZT0_INDEX_MUL_VL,/* ZT0[<imm>], bits [13:12]. */ 988 988 AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ 989 989 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ 990 990 - AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ 991 990 AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ 992 991 AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ 993 992 AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */

-1

opcodes/aarch64-asm-2.c

Reviewed

··· 866 866 case AARCH64_OPND_Em: 867 867 case AARCH64_OPND_Em16: 868 868 case AARCH64_OPND_Em8: 869 869 - case AARCH64_OPND_SM3_IMM2: 870 869 return aarch64_ins_reglane (self, info, code, inst, errors); 871 870 case AARCH64_OPND_Em_INDEX1_14: 872 871 case AARCH64_OPND_Em_INDEX2_13:

-1

opcodes/aarch64-dis-2.c

Reviewed

··· 37851 37851 case AARCH64_OPND_Em: 37852 37852 case AARCH64_OPND_Em16: 37853 37853 case AARCH64_OPND_Em8: 37854 37854 - case AARCH64_OPND_SM3_IMM2: 37855 37854 return aarch64_ext_reglane (self, info, code, inst, errors); 37856 37855 case AARCH64_OPND_Em_INDEX1_14: 37857 37856 case AARCH64_OPND_Em_INDEX2_13:

-1

opcodes/aarch64-opc-2.c

Reviewed

··· 365 365 {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"}, 366 366 {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"}, 367 367 {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, 368 368 - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, 369 368 {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, 370 369 {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, 371 370 {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},

-1

opcodes/aarch64-opc.c

Reviewed

··· 4311 4311 case AARCH64_OPND_Em: 4312 4312 case AARCH64_OPND_Em16: 4313 4313 case AARCH64_OPND_Em8: 4314 4314 - case AARCH64_OPND_SM3_IMM2: 4315 4314 snprintf (buf, size, "%s[%s]", 4316 4315 style_reg (styler, "v%d.%s", opnd->reglane.regno, 4317 4316 aarch64_get_qualifier_name (opnd->qualifier)),

-2

opcodes/aarch64-tbl.h

Reviewed

··· 8674 8674 Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \ 8675 8675 Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ 8676 8676 "a 16-bit unsigned immediate for TME tcancel") \ 8677 8677 - Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ 8678 8678 - "an indexed SM3 vector immediate") \ 8679 8677 /* These next two are really register fields; the [...] notation \ 8680 8678 is just syntactic sugar. */ \ 8681 8679 Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd), \