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[READ-ONLY] Mirror of https://github.com/jmrplens/kleidos. Kleidos — Hardware BLE password manager for ESP32-S3 (M5StickC Plus2, StickS3, M5Stack Gray, T-Deck, Cardputer)
jmrplens.github.io/kleidos/
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kleidos
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test
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hal
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test_rtc_hal_floor_cache
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at
main
2 files
José M. Requena Plens
Close the trust-cache races and tighten the zone validator
11d ago
1821252f
rtc_hal_amalgam.cpp
Close the trust-cache races and tighten the zone validator Consolidated-review remediation for the R1..R4 trust/clock work: - I-1: replace the internal seed-floor cache's boolean valid flag with a generation counter. applyEpoch bumps the generation after persisting the new floor; readSeedFloor snapshots it before the NVS read and publishes only under an unchanged generation, and a cache hit requires the cached generation to be current — a reader that raced a set can no longer latch a stale floor and pin clockTrust at None until reboot. Covered by a new native suite (test/hal/test_rtc_hal_floor_cache) that scripts the exact interleaving through an NvsStore fake hook; the device-only currentEpoch definition is now ESP_PLATFORM-gated so the backend TU links on the host against the injectable epoch provider. - M-1: apply the same generation pattern to the BM8563 VL/integrity cache so an in-flight pre-write chip read cannot overwrite a set's invalidation. - M-2: make s_clockSetThisSession a std::atomic<bool> (relaxed) — it crosses the services/UI cores. - M-3: zoneEntryValid now rejects active DST rules with startMonth == endMonth, which would silently classify via the southern-wraparound branch. - M-4: add a drawClockUnsetChip overload taking the precomputed reserve and use it from the Stick header band, so trust + chip width are evaluated once per paint (no one-frame reserve/draw mismatch on a trust flip). Claude-Session: https://claude.ai/code/session_01SV58JXhfxhhc9DC6vdjBo4
1 week ago
test_rtc_hal_floor_cache.cpp
Close the trust-cache races and tighten the zone validator Consolidated-review remediation for the R1..R4 trust/clock work: - I-1: replace the internal seed-floor cache's boolean valid flag with a generation counter. applyEpoch bumps the generation after persisting the new floor; readSeedFloor snapshots it before the NVS read and publishes only under an unchanged generation, and a cache hit requires the cached generation to be current — a reader that raced a set can no longer latch a stale floor and pin clockTrust at None until reboot. Covered by a new native suite (test/hal/test_rtc_hal_floor_cache) that scripts the exact interleaving through an NvsStore fake hook; the device-only currentEpoch definition is now ESP_PLATFORM-gated so the backend TU links on the host against the injectable epoch provider. - M-1: apply the same generation pattern to the BM8563 VL/integrity cache so an in-flight pre-write chip read cannot overwrite a set's invalidation. - M-2: make s_clockSetThisSession a std::atomic<bool> (relaxed) — it crosses the services/UI cores. - M-3: zoneEntryValid now rejects active DST rules with startMonth == endMonth, which would silently classify via the southern-wraparound branch. - M-4: add a drawClockUnsetChip overload taking the precomputed reserve and use it from the Stick header band, so trust + chip width are evaluated once per paint (no one-frame reserve/draw mismatch on a trust flip). Claude-Session: https://claude.ai/code/session_01SV58JXhfxhhc9DC6vdjBo4
1 week ago