Document the GPS layer, add T-Deck HIL coverage, fix VALSET on real silicon
Add the u-blox M10 introspection chip page and index row, and a HIL suite
(test_gps_layer.py) exercised on the real T-Deck module. The first hardware
run surfaced three genuine M10 behaviors the unit tests could not:
- UBX-CFG-VALSET layers is a bitmask (RAM = bit 0 = 0x01), not the VALGET
layer enum: an all-zero mask writes nowhere and never ACKs, so every
GPSCFG set! silently failed. Fixed + native regression test.
- readStatus must enable periodic NAV-PVT/NAV-SAT/MON-HW UART1 output first:
the M10 boots NMEA-only and ignores on-demand status polls.
- Config/ACK timeouts raised and a VALSET resend budget added, since VALGET/
VALSET now compete with that periodic stream.
Fleet 43/43 -Werror, native 1716/1716, clang-tidy 0, doxygen 0. HIL on the
real u-blox M10: 6 passed / 1 skip (GPSPROBE u-blox M10, GPSSYNC_OK via NVS
fast-path, GPSCFG dump/get/critical-bang read-back-safe, GPSMON).
Claude-Session: https://claude.ai/code/session_01SV58JXhfxhhc9DC6vdjBo4