Add IP5306 and AW9523 register map tables
Add datasheet/community-verified register-map descriptor tables for the
Injoinic IP5306 boost-charger (M5Stack Gray, 13 regs) and the AWINIC
AW9523B I/O expander (CoreS3 SE, 29 regs), feeding the Phase-2
introspection engine (decoded dumps, named-field access, critical write
blocklist). Register both maps on their drivers' begin() success and add
a combined native test suite (validator, floors, anchors, critical
classification, formatRegLine no-truncation fence).
IP5306 0x77 key events are read-to-clear, modeled Access::R with a doc
note; the SYS_CTL1/SYS_CTL2 bit layouts disagree across community maps
and are documented in prose only.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Add IP5306 and AW9523 register map tables
Add datasheet/community-verified register-map descriptor tables for the
Injoinic IP5306 boost-charger (M5Stack Gray, 13 regs) and the AWINIC
AW9523B I/O expander (CoreS3 SE, 29 regs), feeding the Phase-2
introspection engine (decoded dumps, named-field access, critical write
blocklist). Register both maps on their drivers' begin() success and add
a combined native test suite (validator, floors, anchors, critical
classification, formatRegLine no-truncation fence).
IP5306 0x77 key events are read-to-clear, modeled Access::R with a doc
note; the SYS_CTL1/SYS_CTL2 bit layouts disagree across community maps
and are documented in prose only.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Add PMIC temperature, AXP2101 VBUS and AXP192 coulomb accessors
Surface three curated PMIC telemetry accessors, verified against the
X-Powers datasheets and XPowersLib:
- PMIC die temperature (AXP192 0x5E/0x5F: code*0.1-144.7; AXP2101 TDIE
0x3C/0x3D: 22.0+(7274-raw)/20.0), enabled once at begin().
- AXP2101 VBUS voltage (0x38/0x39, 14-bit, 1 mV/LSB).
- AXP192 coulomb gauge net charge in mAh (0xB0-B3 charge minus 0xB4-B7
discharge, scaled by the 0x84 ADC rate; counter enabled at begin()).
Pure decode helpers live in pmic_common.h with datasheet-vector native
tests. Wired through IPmic/PowerManager (false-defaulting), the AXP
manager, RES?/PMIC? debug lines, and capability-probed telemetry
channels (pmic_temp_c, batt_coulomb_mah).
On-device: Plus1 pmic_temp_c=42.4 coulomb=0.0; CoreS3 SE pmic_temp_c=27.4
vbus_mv=5165; StickS3 all three na.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Fix branch-clone, rounding, cast, and remaining long-tail findings
- bugprone-branch-clone (12): fold genuinely identical switch arms
(typing status map, PM1 power levels, wake-cause names, glyph
fallback), merge the duplicated small-panel atlas ladder, rebuild
scaleFor as per-panel constexpr scale tables (lookup-table idiom),
restructure the modal confirm poll around explicit hold/press
predicates (also clears the DeMorgan finding), and NOLINT the one
per-SoC gated ADC calibration switch with rationale.
- bugprone-casting-through-void (13): use direct reinterpret_cast (the
documented pro-type-reinterpret-cast deviation) for byte/sockaddr
views; keep the SPI slot two-step through void* with rationale (it
exists to satisfy -Werror=cast-align next to the static_asserts).
- bugprone-incorrect-roundings (9): std::lroundf instead of +0.5 casts.
- cert-dcl50-cpp (5): rationale NOLINTs on the printf-style formatters
(a parameter pack cannot produce the va_list vsnprintf needs).
- cppcoreguidelines-pro-type-const-cast: const-correct the WordReader
ctx (API + trampoline + tests, const_cast deleted); NOLINT the two
std <cstring>-convention mutable overloads.
- Long tail: explicit void* casts + sizeof(T) rationale in rtos_queue,
range-for loop conversions, 0x80-mask instead of int8_t reinterpret
for the AXP2101 gauge, uint8_t slot subscript, parenthesized -1 pin
macros, extended the __wrap_log_printf ABI suppression to the
reserved-identifier aliases, integer-center tween targets.
Claude-Session: https://claude.ai/code/session_01SV58JXhfxhhc9DC6vdjBo4
Add PMIC temperature, AXP2101 VBUS and AXP192 coulomb accessors
Surface three curated PMIC telemetry accessors, verified against the
X-Powers datasheets and XPowersLib:
- PMIC die temperature (AXP192 0x5E/0x5F: code*0.1-144.7; AXP2101 TDIE
0x3C/0x3D: 22.0+(7274-raw)/20.0), enabled once at begin().
- AXP2101 VBUS voltage (0x38/0x39, 14-bit, 1 mV/LSB).
- AXP192 coulomb gauge net charge in mAh (0xB0-B3 charge minus 0xB4-B7
discharge, scaled by the 0x84 ADC rate; counter enabled at begin()).
Pure decode helpers live in pmic_common.h with datasheet-vector native
tests. Wired through IPmic/PowerManager (false-defaulting), the AXP
manager, RES?/PMIC? debug lines, and capability-probed telemetry
channels (pmic_temp_c, batt_coulomb_mah).
On-device: Plus1 pmic_temp_c=42.4 coulomb=0.0; CoreS3 SE pmic_temp_c=27.4
vbus_mv=5165; StickS3 all three na.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Add IP5306 and AW9523 register map tables
Add datasheet/community-verified register-map descriptor tables for the
Injoinic IP5306 boost-charger (M5Stack Gray, 13 regs) and the AWINIC
AW9523B I/O expander (CoreS3 SE, 29 regs), feeding the Phase-2
introspection engine (decoded dumps, named-field access, critical write
blocklist). Register both maps on their drivers' begin() success and add
a combined native test suite (validator, floors, anchors, critical
classification, formatRegLine no-truncation fence).
IP5306 0x77 key events are read-to-clear, modeled Access::R with a doc
note; the SYS_CTL1/SYS_CTL2 bit layouts disagree across community maps
and are documented in prose only.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Remove the M5Stack Gray variant from the fleet
The M5Stack Gray is retired (owner-approved): the fleet drops from 9 to 8
device variants. This removes the Gray as a build target / device while
keeping every reusable driver and HAL layer intact.
Removed (Gray-exclusive wiring only):
- variants/m5stack_gray/ (variant.h, ini, sdkconfig, the four envs)
- src/boards/board_gray.cpp (the DEVICE_ID==5 board-registry factory)
- the web installer mockup (gray.svg + screen png) and app.js entry
- docs/hardware/devices/m5stack-gray.md and every fleet-list / inventory
/ identifier / secure-availability row across docs, CI, and instructions
Kept (per owner: preserve tested drivers/HAL even with no current consumer):
- the IP5306 PMIC driver family (src/drivers/power/ip5306*) — Gray was its
only board; still native-validated by test_small_pmic_regmaps
- the classic-ESP32 RTC_CNTL MMIO regmap (rtc_cntl_esp32_regmap.h) — Gray
was the only classic internal-RTC board; still native-validated
- board_gray_log_wrap.cpp renamed to board_log_printf_wrap.cpp: the
__wrap_log_printf stub is fleet-wide (esp32_base defines the gate), not
Gray-specific
DEVICE_ID 5 is retired and left unused so the remaining ids stay stable.
CI covering set rebalanced (Gray was the classic-ESP32 representative):
sticks3, tdeck, cores3_se, m5core_ink, m5stickc_plus2. m5stickc_plus2
(classic ESP32 + ST7789 full-frame polling + 8 MB OTA) replaces the Gray's
classic-ESP32 + OTA + polling coverage. core2_v13 is intentionally not added
to CI: it is an "Initial" WIP board that currently overflows DRAM at link
(pre-existing), so it cannot be a green gate member.
Native tests 2306/2306. Base envs build green for the new CI set
(sticks3, m5stickc_plus2, tdeck, cores3_se, m5core_ink).
Claude-Session: https://claude.ai/code/session_01P6BNTpbgrvnZXSJnNuj8ZJ
Remove the M5Stack Gray variant from the fleet
The M5Stack Gray is retired (owner-approved): the fleet drops from 9 to 8
device variants. This removes the Gray as a build target / device while
keeping every reusable driver and HAL layer intact.
Removed (Gray-exclusive wiring only):
- variants/m5stack_gray/ (variant.h, ini, sdkconfig, the four envs)
- src/boards/board_gray.cpp (the DEVICE_ID==5 board-registry factory)
- the web installer mockup (gray.svg + screen png) and app.js entry
- docs/hardware/devices/m5stack-gray.md and every fleet-list / inventory
/ identifier / secure-availability row across docs, CI, and instructions
Kept (per owner: preserve tested drivers/HAL even with no current consumer):
- the IP5306 PMIC driver family (src/drivers/power/ip5306*) — Gray was its
only board; still native-validated by test_small_pmic_regmaps
- the classic-ESP32 RTC_CNTL MMIO regmap (rtc_cntl_esp32_regmap.h) — Gray
was the only classic internal-RTC board; still native-validated
- board_gray_log_wrap.cpp renamed to board_log_printf_wrap.cpp: the
__wrap_log_printf stub is fleet-wide (esp32_base defines the gate), not
Gray-specific
DEVICE_ID 5 is retired and left unused so the remaining ids stay stable.
CI covering set rebalanced (Gray was the classic-ESP32 representative):
sticks3, tdeck, cores3_se, m5core_ink, m5stickc_plus2. m5stickc_plus2
(classic ESP32 + ST7789 full-frame polling + 8 MB OTA) replaces the Gray's
classic-ESP32 + OTA + polling coverage. core2_v13 is intentionally not added
to CI: it is an "Initial" WIP board that currently overflows DRAM at link
(pre-existing), so it cannot be a green gate member.
Native tests 2306/2306. Base envs build green for the new CI set
(sticks3, m5stickc_plus2, tdeck, cores3_se, m5core_ink).
Claude-Session: https://claude.ai/code/session_01P6BNTpbgrvnZXSJnNuj8ZJ
Remove the M5Stack Gray variant from the fleet
The M5Stack Gray is retired (owner-approved): the fleet drops from 9 to 8
device variants. This removes the Gray as a build target / device while
keeping every reusable driver and HAL layer intact.
Removed (Gray-exclusive wiring only):
- variants/m5stack_gray/ (variant.h, ini, sdkconfig, the four envs)
- src/boards/board_gray.cpp (the DEVICE_ID==5 board-registry factory)
- the web installer mockup (gray.svg + screen png) and app.js entry
- docs/hardware/devices/m5stack-gray.md and every fleet-list / inventory
/ identifier / secure-availability row across docs, CI, and instructions
Kept (per owner: preserve tested drivers/HAL even with no current consumer):
- the IP5306 PMIC driver family (src/drivers/power/ip5306*) — Gray was its
only board; still native-validated by test_small_pmic_regmaps
- the classic-ESP32 RTC_CNTL MMIO regmap (rtc_cntl_esp32_regmap.h) — Gray
was the only classic internal-RTC board; still native-validated
- board_gray_log_wrap.cpp renamed to board_log_printf_wrap.cpp: the
__wrap_log_printf stub is fleet-wide (esp32_base defines the gate), not
Gray-specific
DEVICE_ID 5 is retired and left unused so the remaining ids stay stable.
CI covering set rebalanced (Gray was the classic-ESP32 representative):
sticks3, tdeck, cores3_se, m5core_ink, m5stickc_plus2. m5stickc_plus2
(classic ESP32 + ST7789 full-frame polling + 8 MB OTA) replaces the Gray's
classic-ESP32 + OTA + polling coverage. core2_v13 is intentionally not added
to CI: it is an "Initial" WIP board that currently overflows DRAM at link
(pre-existing), so it cannot be a green gate member.
Native tests 2306/2306. Base envs build green for the new CI set
(sticks3, m5stickc_plus2, tdeck, cores3_se, m5core_ink).
Claude-Session: https://claude.ai/code/session_01P6BNTpbgrvnZXSJnNuj8ZJ
Add M5PM1 PY32 register map table
Introspection descriptor table for the M5StickC Plus S3's custom
PY32-based M5PM1 PMIC (I2C 0x6E), feeding the generic regmap engine.
The M5PM1 has no public datasheet. Every entry is confirmed against the
repo's hardware-validated py32_pmic_regs.h / py32_pmic.cpp (mirrored from
M5GFX board_M5StickS3), independently cross-checked against Espressif's
esp-claw StickS3 power_manager.c (0x09 I2C config, 0x10/0x11/0x13/0x16
GPIO block, PYG2/PYG3 rail masks) and M5Stack docs (PYG0..PYG4 mapping).
Field tables only where the bit layout is hardware-confirmed; everything
else is prose. Criticals flag rail/power-off/timed-power-on/download-lock
registers (0x06, 0x07, 0x0C, 0x10/0x11/0x13/0x16, 0x3C, 0x3D, 0x49, 0x4A).
py32_pmic.cpp now registers the table after ready_ = true and logs the
DeviceId/Model identity bytes (previously read but discarded); boot is
not gated on them. Native test mirrors test_axp192_regmap: validator,
floor >= 20, anchors, criticals, no-truncation sweep.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY
Clear SonarCloud maintainability issues in hal/drivers/crypto/vault/platform/web
Mechanical/behaviour-preserving fixes (const-correctness, type→auto, byte-buffer→
std::array, param packs, dead stores, cognitive complexity via extracted helpers
e.g. pbkdf2DeriveBlock) across hal, drivers, crypto, vault, platform, ota, web,
main. No functional/crypto-semantic change.
Claude-Session: https://claude.ai/code/session_01Y7Cy1HetRp6TZAUAeekN8X
Add M5PM1 PY32 register map table
Introspection descriptor table for the M5StickC Plus S3's custom
PY32-based M5PM1 PMIC (I2C 0x6E), feeding the generic regmap engine.
The M5PM1 has no public datasheet. Every entry is confirmed against the
repo's hardware-validated py32_pmic_regs.h / py32_pmic.cpp (mirrored from
M5GFX board_M5StickS3), independently cross-checked against Espressif's
esp-claw StickS3 power_manager.c (0x09 I2C config, 0x10/0x11/0x13/0x16
GPIO block, PYG2/PYG3 rail masks) and M5Stack docs (PYG0..PYG4 mapping).
Field tables only where the bit layout is hardware-confirmed; everything
else is prose. Criticals flag rail/power-off/timed-power-on/download-lock
registers (0x06, 0x07, 0x0C, 0x10/0x11/0x13/0x16, 0x3C, 0x3D, 0x49, 0x4A).
py32_pmic.cpp now registers the table after ready_ = true and logs the
DeviceId/Model identity bytes (previously read but discarded); boot is
not gated on them. Native test mirrors test_axp192_regmap: validator,
floor >= 20, anchors, criticals, no-truncation sweep.
Claude-Session: https://claude.ai/code/session_01Ciw3Ea5Bb2YAcmuZ1dywRY